pa.md (parallel_addb, [...]): New patterns.
* pa.md (parallel_addb, parallel_movb): New patterns.
(fmpyadd, fmpysub): New patterns.
From-SVN: r12384
This commit is contained in:
Jeff Law
parent
d85ab9665c
commit
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1 changed files with 138 additions and 0 deletions
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@ -4965,6 +4965,144 @@
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(const_int 8)
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(const_int 12)))))])
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;; The next several patterns (parallel_addb, parallel_movb, fmpyadd and
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;; fmpysub aren't currently used by the FSF sources, but will be soon.
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;;
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;; They're in the FSF tree for documentation and to make Cygnus<->FSF
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;; merging easier.
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(define_insn ""
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[(set (pc) (label_ref (match_operand 3 "" "" )))
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(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
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"reload_completed && operands[0] == operands[1] || operands[0] == operands[2]"
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"*
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{
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return output_parallel_addb (operands, get_attr_length (insn));
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}"
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[(set_attr "type" "parallel_branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
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(const_int 8184))
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(const_int 4)
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(const_int 8)))])
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(define_insn ""
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[(set (pc) (label_ref (match_operand 2 "" "" )))
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(set (match_operand:SF 0 "register_operand" "=r")
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(match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
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"reload_completed"
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"*
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{
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return output_parallel_movb (operands, get_attr_length (insn));
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}"
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[(set_attr "type" "parallel_branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
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(const_int 8184))
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(const_int 4)
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(const_int 8)))])
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(define_insn ""
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[(set (pc) (label_ref (match_operand 2 "" "" )))
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(set (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
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"reload_completed"
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"*
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{
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return output_parallel_movb (operands, get_attr_length (insn));
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}"
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[(set_attr "type" "parallel_branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
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(const_int 8184))
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(const_int 4)
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(const_int 8)))])
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(define_insn ""
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[(set (pc) (label_ref (match_operand 2 "" "" )))
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(set (match_operand:HI 0 "register_operand" "=r")
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(match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
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"reload_completed"
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"*
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{
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return output_parallel_movb (operands, get_attr_length (insn));
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}"
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[(set_attr "type" "parallel_branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
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(const_int 8184))
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(const_int 4)
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(const_int 8)))])
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(define_insn ""
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[(set (pc) (label_ref (match_operand 2 "" "" )))
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(set (match_operand:QI 0 "register_operand" "=r")
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(match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
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"reload_completed"
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"*
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{
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return output_parallel_movb (operands, get_attr_length (insn));
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}"
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[(set_attr "type" "parallel_branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
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(const_int 8184))
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(const_int 4)
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(const_int 8)))])
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;; These insns will replace fmpyadd and fmpysub peepholes when the
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;; independent insn combination code is installed at the FSF. Until
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;; then these patterns aren't used by the FSF compiler and are only
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;; here for documentation purposes.
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(define_insn ""
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[(set (match_operand 0 "register_operand" "=f")
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(mult (match_operand 1 "register_operand" "f")
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(match_operand 2 "register_operand" "f")))
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(set (match_operand 3 "register_operand" "+f")
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(plus (match_operand 4 "register_operand" "f")
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(match_operand 5 "register_operand" "f")))]
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"TARGET_SNAKE && ! TARGET_SOFT_FLOAT
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&& reload_completed && fmpyaddoperands (operands)"
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"*
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{
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if (GET_MODE (operands[0]) == DFmode)
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{
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if (rtx_equal_p (operands[3], operands[5]))
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return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
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else
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return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
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}
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else
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{
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if (rtx_equal_p (operands[3], operands[5]))
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return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
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else
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return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
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}
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}"
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[(set_attr "type" "fpalu")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand 0 "register_operand" "=f")
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(mult (match_operand 1 "register_operand" "f")
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(match_operand 2 "register_operand" "f")))
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(set (match_operand 3 "register_operand" "+f")
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(minus (match_operand 4 "register_operand" "f")
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(match_operand 5 "register_operand" "f")))]
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"TARGET_SNAKE && ! TARGET_SOFT_FLOAT
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&& reload_completed && fmpysuboperands (operands)"
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"*
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{
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if (GET_MODE (operands[0]) == DFmode)
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return \"fmpysub,dbl %1,%2,%0,%5,%3\";
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else
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return \"fmpysub,sgl %1,%2,%0,%5,%3\";
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}"
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[(set_attr "type" "fpalu")
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(set_attr "length" "4")])
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;; The next four peepholes take advantage of the new 5 operand
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;; fmpy{add,sub} instructions available on 1.1 CPUS. Basically
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;; fmpyadd performs a multiply and add/sub of independent operands
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