i386.c (ix86_decompose_address): Use simplify_gen_subreg to generate SImode equivalent of address...
* config/i386/i386.c (ix86_decompose_address): Use simplify_gen_subreg to generate SImode equivalent of address, zero-extended with AND RTX. * config/i386/i386.md (ashift to lea splitter): Split to SImode mult. (simple lea to add/shift peephole2s): Remove peephole2s that operate on subregs of DImode operations. From-SVN: r192908
This commit is contained in:
Uros Bizjak
parent
bc3591eb9f
commit
df65258575
3 changed files with 19 additions and 87 deletions
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@ -1,10 +1,17 @@
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2012-10-29 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c (ix86_decompose_address): Use simplify_gen_subreg
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to generate SImode equivalent of address, zero-extended with AND RTX.
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* config/i386/i386.md (ashift to lea splitter): Split to SImode mult.
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(simple lea to add/shift peephole2s): Remove peephole2s that operate
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on subregs of DImode operations.
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2012-10-28 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimization/55106
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* lra-constraints.c (skip_usage_debug_insns): New function.
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(check_secondary_memory_needed_p): Ditto.
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(inherit_reload_reg): Use the new functions. Improve debug
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output.
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(inherit_reload_reg): Use the new functions. Improve debug output.
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2012-10-29 Jonathan Wakely <jwakely.gcc@gmail.com>
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@ -47,7 +54,8 @@
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* ipa-inline.c (edge_badness): Reduce precision; use scc hints.
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(inline_small_functions): Fix dumps; update all callees after inlining.
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* ipa-inline.h (INLINE_HINT_in_scc, INLINE_HINT_same_scc): New constants.
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* ipa-inline.h (INLINE_HINT_in_scc, INLINE_HINT_same_scc): New
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constants.
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(inline summary): Add SCC_NO.
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* ipa-inline-analysis.c (dump_inline_hints): Dump SCC hints.
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(reset_inline_summary): Reset scc_no.
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@ -11821,7 +11821,11 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
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return 0;
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}
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else if (GET_MODE (addr) == DImode)
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addr = gen_rtx_SUBREG (SImode, addr, 0);
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{
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addr = simplify_gen_subreg (SImode, addr, DImode, 0);
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if (addr == NULL_RTX)
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return 0;
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}
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else if (GET_MODE (addr) != VOIDmode)
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return 0;
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}
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@ -9600,10 +9600,10 @@
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"TARGET_64BIT && reload_completed
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&& true_regnum (operands[0]) != true_regnum (operands[1])"
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[(set (match_dup 0)
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(zero_extend:DI (subreg:SI (mult:DI (match_dup 1) (match_dup 2)) 0)))]
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(zero_extend:DI (mult:SI (match_dup 1) (match_dup 2))))]
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{
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
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})
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;; This pattern can't accept a variable shift count, since shifts by
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@ -17357,28 +17357,6 @@
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[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])])
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand")
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(subreg:SI (plus:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "nonmemory_operand")) 0))]
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"TARGET_64BIT && !TARGET_OPT_AGU
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&& REGNO (operands[0]) == REGNO (operands[1])
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = gen_lowpart (SImode, operands[2]);")
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand")
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(subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
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(match_operand:DI 2 "register_operand")) 0))]
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"TARGET_64BIT && !TARGET_OPT_AGU
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&& REGNO (operands[0]) == REGNO (operands[2])
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[1] = gen_lowpart (SImode, operands[1]);")
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI
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@ -17403,36 +17381,6 @@
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(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))])])
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI
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(subreg:SI (plus:DI (match_dup 0)
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(match_operand:DI 1 "nonmemory_operand")) 0)))]
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"TARGET_64BIT && !TARGET_OPT_AGU
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[2] = gen_lowpart (SImode, operands[0]);
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})
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI
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(subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
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(match_dup 0)) 0)))]
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"TARGET_64BIT && !TARGET_OPT_AGU
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[2] = gen_lowpart (SImode, operands[0]);
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})
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(define_peephole2
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[(set (match_operand:SWI48 0 "register_operand")
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(mult:SWI48 (match_dup 0)
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@ -17443,18 +17391,6 @@
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(clobber (reg:CC FLAGS_REG))])]
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"operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand")
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(subreg:SI (mult:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "const_int_operand")) 0))]
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"TARGET_64BIT
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&& exact_log2 (INTVAL (operands[2])) >= 0
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&& REGNO (operands[0]) == REGNO (operands[1])
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI
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@ -17469,22 +17405,6 @@
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand")
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(zero_extend:DI
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(subreg:SI (mult:DI (match_dup 0)
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(match_operand:DI 1 "const_int_operand")) 0)))]
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"TARGET_64BIT
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&& exact_log2 (INTVAL (operands[2])) >= 0
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(zero_extend:DI (ashift:SI (match_dup 2) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
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operands[2] = gen_lowpart (SImode, operands[0]);
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})
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;; The ESP adjustments can be done by the push and pop instructions. Resulting
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;; code is shorter, since push is only 1 byte, while add imm, %esp is 3 bytes.
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;; On many CPUs it is also faster, since special hardware to avoid esp
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