From def72bd2e9c6d7b92791b19a249256e1ede33c32 Mon Sep 17 00:00:00 2001
From: Gavin Romig-Koch <gavin@cygnus.com>
Date: Wed, 3 Feb 1999 13:04:22 +0000
Subject: [PATCH] mips.c (true_reg_or_0_operand): New function.

	* config/mips/mips.c (true_reg_or_0_operand) : New function.
	* config/mips/mips.h (PREDICATE_CODES): Add true_reg_or_0_operand.
	* config/mips/mips.md (div_trap,div_trap_normal,div_trap_mips16):
	Use true_reg_or_0_operand for div_trap.

From-SVN: r25008
---
 gcc/ChangeLog           |  7 +++++++
 gcc/config/mips/mips.c  | 27 +++++++++++++++++++++++++++
 gcc/config/mips/mips.h  |  6 ++++--
 gcc/config/mips/mips.md |  6 +++---
 4 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 95de3cb4c9c..15187853b2e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Wed Feb  3 15:51:04 1999  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* config/mips/mips.c (true_reg_or_0_operand) : New function.
+	* config/mips/mips.h (PREDICATE_CODES): Add true_reg_or_0_operand.
+	* config/mips/mips.md (div_trap,div_trap_normal,div_trap_mips16): 
+	Use true_reg_or_0_operand for div_trap.
+
 Wed Feb  3 20:44:59 1999  J"orn Rennecke <amylaar@cygnus.co.uk>
 
 	* loop.h (express_from): Declare.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index d713550f68b..e569c3608a8 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -543,6 +543,33 @@ reg_or_0_operand (op, mode)
   return 0;
 }
 
+/* Return truth value of whether OP is a register or the constant 0,
+   even in mips16 mode. */
+
+int
+true_reg_or_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case CONST_INT:
+      return INTVAL (op) == 0;
+
+    case CONST_DOUBLE:
+      return op == CONST0_RTX (mode);
+
+    case REG:
+    case SUBREG:
+      return register_operand (op, mode);
+
+    default:
+      break;
+    }
+
+  return 0;
+}
+
 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
 
 int
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 091a841c5ca..0fd87c73e48 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -226,6 +226,7 @@ extern void		print_operand_address ();
 extern void		print_operand ();
 extern void		print_options ();
 extern int		reg_or_0_operand ();
+extern int		true_reg_or_0_operand ();
 extern int		simple_epilogue_p ();
 extern int		simple_memory_operand ();
 extern int		double_memory_operand ();
@@ -3697,7 +3698,8 @@ while (0)
   {"uns_arith_operand",		{ REG, CONST_INT, SUBREG }},		\
   {"arith_operand",		{ REG, CONST_INT, SUBREG }},		\
   {"arith32_operand",		{ REG, CONST_INT, SUBREG }},		\
-  {"reg_or_0_operand",		{ REG, CONST_INT, SUBREG }},		\
+  {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
+  {"true_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
   {"small_int",			{ CONST_INT }},				\
   {"large_int",			{ CONST_INT }},				\
   {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
@@ -3715,7 +3717,7 @@ while (0)
 				  SYMBOL_REF, LABEL_REF, SUBREG, REG,	\
 				  MEM, SIGN_EXTEND }},			\
   {"se_register_operand",	{ SUBREG, REG, SIGN_EXTEND }},		\
-  {"se_reg_or_0_operand",	{ REG, CONST_INT, SUBREG,		\
+  {"se_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG,	\
 				  SIGN_EXTEND }},			\
   {"se_uns_arith_operand",	{ REG, CONST_INT, SUBREG,		\
 				  SIGN_EXTEND }},			\
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 2715f1f9c73..40e741975b0 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2414,7 +2414,7 @@
 
 (define_expand "div_trap"
   [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "reg_or_0_operand" "dJ"))
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
             (match_operand 2 "immediate_operand" ""))]
   ""
   "
@@ -2428,7 +2428,7 @@
 
 (define_insn "div_trap_normal"
   [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "reg_or_0_operand" "dJ"))
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
             (match_operand 2 "immediate_operand" ""))]
   "!TARGET_MIPS16"
   "*
@@ -2471,7 +2471,7 @@
 
 (define_insn "div_trap_mips16"
   [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "reg_or_0_operand" "dJ"))
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
             (match_operand 2 "immediate_operand" ""))
    (clobber (reg:SI 24))]
   "TARGET_MIPS16"