amdgcn: switch mov insns to compact syntax
The move instructions typically have many alternatives (and I'm about to add more) so are good candidates for the new syntax. This patch only converts the patterns where there are no significant changes to the generated files. The other patterns can be converted another time. gcc/ChangeLog: * config/gcn/gcn-valu.md (*mov<mode>): Convert to compact syntax. (mov<mode>_exec): Likewise. (mov<mode>_sgprbase): Likewise. * config/gcn/gcn.md (*mov<mode>_insn): Likewise. (*movti_insn): Likewise.
This commit is contained in:
Andrew Stubbs
parent
eb239c7f22
commit
ddfa43933e
2 changed files with 106 additions and 128 deletions
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@ -457,23 +457,21 @@
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(set_attr "length" "4,8")])
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(define_insn "mov<mode>_exec"
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[(set (match_operand:V_1REG 0 "nonimmediate_operand" "=v, v, v, v, v, m")
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[(set (match_operand:V_1REG 0 "nonimmediate_operand")
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(vec_merge:V_1REG
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(match_operand:V_1REG 1 "general_operand" "vA, B, v,vA, m, v")
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(match_operand:V_1REG 2 "gcn_alu_or_unspec_operand"
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"U0,U0,vA,vA,U0,U0")
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(match_operand:DI 3 "register_operand" " e, e,cV,Sv, e, e")))
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(clobber (match_scratch:<VnDI> 4 "=X, X, X, X,&v,&v"))]
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(match_operand:V_1REG 1 "general_operand")
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(match_operand:V_1REG 2 "gcn_alu_or_unspec_operand")
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(match_operand:DI 3 "register_operand")))
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(clobber (match_scratch:<VnDI> 4))]
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"!MEM_P (operands[0]) || REG_P (operands[1])"
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"@
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v_mov_b32\t%0, %1
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v_mov_b32\t%0, %1
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v_cndmask_b32\t%0, %2, %1, vcc
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v_cndmask_b32\t%0, %2, %1, %3
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#
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#"
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[(set_attr "type" "vop1,vop1,vop2,vop3a,*,*")
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(set_attr "length" "4,8,4,8,16,16")])
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{@ [cons: =0, 1, 2, 3, =4; attrs: type, length]
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[v,vA,U0,e ,X ;vop1 ,4 ] v_mov_b32\t%0, %1
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[v,B ,U0,e ,X ;vop1 ,8 ] v_mov_b32\t%0, %1
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[v,v ,vA,cV,X ;vop2 ,4 ] v_cndmask_b32\t%0, %2, %1, vcc
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[v,vA,vA,Sv,X ;vop3a,8 ] v_cndmask_b32\t%0, %2, %1, %3
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[v,m ,U0,e ,&v;* ,16] #
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[m,v ,U0,e ,&v;* ,16] #
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})
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; This variant does not accept an unspec, but does permit MEM
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; read/modify/write which is necessary for maskstore.
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@ -644,19 +642,18 @@
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; flat_load v, vT
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(define_insn "mov<mode>_sgprbase"
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[(set (match_operand:V_1REG 0 "nonimmediate_operand" "= v, v, v, m")
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[(set (match_operand:V_1REG 0 "nonimmediate_operand")
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(unspec:V_1REG
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[(match_operand:V_1REG 1 "general_operand" " vA,vB, m, v")]
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[(match_operand:V_1REG 1 "general_operand")]
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UNSPEC_SGPRBASE))
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(clobber (match_operand:<VnDI> 2 "register_operand" "=&v,&v,&v,&v"))]
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(clobber (match_operand:<VnDI> 2 "register_operand"))]
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"lra_in_progress || reload_completed"
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"@
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v_mov_b32\t%0, %1
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v_mov_b32\t%0, %1
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#
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#"
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[(set_attr "type" "vop1,vop1,*,*")
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(set_attr "length" "4,8,12,12")])
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{@ [cons: =0, 1, =2; attrs: type, length]
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[v,vA,&v;vop1,4 ] v_mov_b32\t%0, %1
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[v,vB,&v;vop1,8 ] ^
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[v,m ,&v;* ,12] #
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[m,v ,&v;* ,12] #
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})
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(define_insn "mov<mode>_sgprbase"
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[(set (match_operand:V_2REG 0 "nonimmediate_operand" "= v, v, m")
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@ -676,17 +673,17 @@
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(set_attr "length" "8,12,12")])
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(define_insn "mov<mode>_sgprbase"
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[(set (match_operand:V_4REG 0 "nonimmediate_operand" "= v, v, m")
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[(set (match_operand:V_4REG 0 "nonimmediate_operand")
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(unspec:V_4REG
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[(match_operand:V_4REG 1 "general_operand" "vDB, m, v")]
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[(match_operand:V_4REG 1 "general_operand")]
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UNSPEC_SGPRBASE))
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(clobber (match_operand:<VnDI> 2 "register_operand" "=&v,&v,&v"))]
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(clobber (match_operand:<VnDI> 2 "register_operand"))]
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"lra_in_progress || reload_completed"
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"v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1
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#
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#"
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[(set_attr "type" "vmult,*,*")
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(set_attr "length" "8,12,12")])
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{@ [cons: =0, 1, =2; attrs: type, length]
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[v,vDB,&v;vmult,8 ] v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1
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[v,m ,&v;* ,12] #
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[m,v ,&v;* ,12] #
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})
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; reload_in was once a standard name, but here it's only referenced by
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; gcn_secondary_reload. It allows a reload with a scratch register.
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@ -542,87 +542,76 @@
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; 32bit move pattern
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(define_insn "*mov<mode>_insn"
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[(set (match_operand:SISF 0 "nonimmediate_operand"
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"=SD,SD,SD,SD,RB,Sm,RS,v,Sg, v, v,RF,v,RLRG, v,SD, v,RM")
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(match_operand:SISF 1 "gcn_load_operand"
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"SSA, J, B,RB,Sm,RS,Sm,v, v,Sv,RF, v,B, v,RLRG, Y,RM, v"))]
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[(set (match_operand:SISF 0 "nonimmediate_operand")
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(match_operand:SISF 1 "gcn_load_operand"))]
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""
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"@
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s_mov_b32\t%0, %1
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s_movk_i32\t%0, %1
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s_mov_b32\t%0, %1
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s_buffer_load%s0\t%0, s[0:3], %1\;s_waitcnt\tlgkmcnt(0)
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s_buffer_store%s1\t%1, s[0:3], %0
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s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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s_store_dword\t%1, %A0
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v_mov_b32\t%0, %1
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store_dword\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
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ds_write_b32\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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ds_read_b32\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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s_mov_b32\t%0, %1
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global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store_dword\t%A0, %1%O0%g0"
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[(set_attr "type" "sop1,sopk,sop1,smem,smem,smem,smem,vop1,vop3a,vop3a,flat,
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flat,vop1,ds,ds,sop1,flat,flat")
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(set_attr "exec" "*,*,*,*,*,*,*,*,none,none,*,*,*,*,*,*,*,*")
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(set_attr "length" "4,4,8,12,12,12,12,4,8,8,12,12,8,12,12,8,12,12")])
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{@ [cons: =0, 1; attrs: type, exec, length]
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[SD ,SSA ;sop1 ,* ,4 ] s_mov_b32\t%0, %1
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[SD ,J ;sopk ,* ,4 ] s_movk_i32\t%0, %1
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[SD ,B ;sop1 ,* ,8 ] s_mov_b32\t%0, %1
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[SD ,RB ;smem ,* ,12] s_buffer_load%s0\t%0, s[0:3], %1\;s_waitcnt\tlgkmcnt(0)
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[RB ,Sm ;smem ,* ,12] s_buffer_store%s1\t%1, s[0:3], %0
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[Sm ,RS ;smem ,* ,12] s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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[RS ,Sm ;smem ,* ,12] s_store_dword\t%1, %A0
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[v ,v ;vop1 ,* ,4 ] v_mov_b32\t%0, %1
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[Sg ,v ;vop3a,none,8 ] v_readlane_b32\t%0, %1, 0
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[v ,Sv ;vop3a,none,8 ] v_writelane_b32\t%0, %1, 0
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[v ,RF ;flat ,* ,12] flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0
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[RF ,v ;flat ,* ,12] flat_store_dword\t%A0, %1%O0%g0
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[v ,B ;vop1 ,* ,8 ] v_mov_b32\t%0, %1
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[RLRG,v ;ds ,* ,12] ds_write_b32\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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[v ,RLRG;ds ,* ,12] ds_read_b32\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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[SD ,Y ;sop1 ,* ,8 ] s_mov_b32\t%0, %1
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[v ,RM ;flat ,* ,12] global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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[RM ,v ;flat ,* ,12] global_store_dword\t%A0, %1%O0%g0
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})
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; 8/16bit move pattern
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; TODO: implement combined load and zero_extend, but *only* for -msram-ecc=on
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(define_insn "*mov<mode>_insn"
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[(set (match_operand:QIHI 0 "nonimmediate_operand"
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"=SD,SD,SD,v,Sg, v, v,RF,v,RLRG, v, v,RM")
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(match_operand:QIHI 1 "gcn_load_operand"
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"SSA, J, B,v, v,Sv,RF, v,B, v,RLRG,RM, v"))]
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[(set (match_operand:QIHI 0 "nonimmediate_operand")
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(match_operand:QIHI 1 "gcn_load_operand"))]
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"gcn_valid_move_p (<MODE>mode, operands[0], operands[1])"
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"@
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s_mov_b32\t%0, %1
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s_movk_i32\t%0, %1
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s_mov_b32\t%0, %1
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v_mov_b32\t%0, %1
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load%o1\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store%s0\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
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ds_write%b0\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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ds_read%u1\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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global_load%o1\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store%s0\t%A0, %1%O0%g0"
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[(set_attr "type"
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"sop1,sopk,sop1,vop1,vop3a,vop3a,flat,flat,vop1,ds,ds,flat,flat")
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(set_attr "exec" "*,*,*,*,none,none,*,*,*,*,*,*,*")
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(set_attr "length" "4,4,8,4,4,4,12,12,8,12,12,12,12")])
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{@ [cons: =0, 1; attrs: type, exec, length]
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[SD ,SSA ;sop1 ,* ,4 ] s_mov_b32\t%0, %1
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[SD ,J ;sopk ,* ,4 ] s_movk_i32\t%0, %1
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[SD ,B ;sop1 ,* ,8 ] s_mov_b32\t%0, %1
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[v ,v ;vop1 ,* ,4 ] v_mov_b32\t%0, %1
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[Sg ,v ;vop3a,none,4 ] v_readlane_b32\t%0, %1, 0
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[v ,Sv ;vop3a,none,4 ] v_writelane_b32\t%0, %1, 0
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[v ,RF ;flat ,* ,12] flat_load%o1\t%0, %A1%O1%g1\;s_waitcnt\t0
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[RF ,v ;flat ,* ,12] flat_store%s0\t%A0, %1%O0%g0
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[v ,B ;vop1 ,* ,8 ] v_mov_b32\t%0, %1
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[RLRG,v ;ds ,* ,12] ds_write%b0\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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[v ,RLRG;ds ,* ,12] ds_read%u1\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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[v ,RM ;flat ,* ,12] global_load%o1\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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[RM ,v ;flat ,* ,12] global_store%s0\t%A0, %1%O0%g0
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})
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; 64bit move pattern
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(define_insn_and_split "*mov<mode>_insn"
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[(set (match_operand:DIDF 0 "nonimmediate_operand"
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"=SD,SD,SD,RS,Sm,v, v,Sg, v, v,RF,RLRG, v, v,RM")
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(match_operand:DIDF 1 "general_operand"
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"SSA, C,DB,Sm,RS,v,DB, v,Sv,RF, v, v,RLRG,RM, v"))]
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[(set (match_operand:DIDF 0 "nonimmediate_operand")
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(match_operand:DIDF 1 "general_operand"))]
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"GET_CODE(operands[1]) != SYMBOL_REF"
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"@
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s_mov_b64\t%0, %1
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s_mov_b64\t%0, %1
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#
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s_store_dwordx2\t%1, %A0
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s_load_dwordx2\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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#
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#
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#
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#
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flat_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store_dwordx2\t%A0, %1%O0%g0
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ds_write_b64\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store_dwordx2\t%A0, %1%O0%g0"
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{@ [cons: =0, 1; attrs: type, length]
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[SD ,SSA ;sop1 ,4 ] s_mov_b64\t%0, %1
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[SD ,C ;sop1 ,8 ] ^
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[SD ,DB ;mult ,* ] #
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[RS ,Sm ;smem ,12] s_store_dwordx2\t%1, %A0
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[Sm ,RS ;smem ,12] s_load_dwordx2\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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[v ,v ;vmult,* ] #
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[v ,DB ;vmult,* ] #
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[Sg ,v ;vmult,* ] #
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[v ,Sv ;vmult,* ] #
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[v ,RF ;flat ,12] flat_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\t0
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[RF ,v ;flat ,12] flat_store_dwordx2\t%A0, %1%O0%g0
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[RLRG,v ;ds ,12] ds_write_b64\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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[v ,RLRG;ds ,12] ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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[v ,RM ;flat ,12] global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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[RM ,v ;flat ,12] global_store_dwordx2\t%A0, %1%O0%g0
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}
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"reload_completed
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&& ((!MEM_P (operands[0]) && !MEM_P (operands[1])
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&& !gcn_sgpr_move_p (operands[0], operands[1]))
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@ -651,32 +640,28 @@
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operands[2] = outhi;
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operands[3] = inhi;
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}
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}
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[(set_attr "type" "sop1,sop1,mult,smem,smem,vmult,vmult,vmult,vmult,flat,
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flat,ds,ds,flat,flat")
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(set_attr "length" "4,8,*,12,12,*,*,*,*,12,12,12,12,12,12")])
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})
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; 128-bit move.
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(define_insn_and_split "*movti_insn"
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[(set (match_operand:TI 0 "nonimmediate_operand"
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"=SD,RS,Sm,RF, v,v, v,SD,RM, v,RL, v")
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(match_operand:TI 1 "general_operand"
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"SSB,Sm,RS, v,RF,v,Sv, v, v,RM, v,RL"))]
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[(set (match_operand:TI 0 "nonimmediate_operand")
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(match_operand:TI 1 "general_operand" ))]
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""
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"@
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#
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s_store_dwordx4\t%1, %A0
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s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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flat_store_dwordx4\t%A0, %1%O0%g0
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flat_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\t0
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#
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#
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#
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global_store_dwordx4\t%A0, %1%O0%g0
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global_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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ds_write_b128\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)"
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{@ [cons: =0, 1; attrs: type, delayeduse, length]
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[SD,SSB;mult ,* ,* ] #
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[RS,Sm ;smem ,* ,12] s_store_dwordx4\t%1, %A0
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[Sm,RS ;smem ,yes,12] s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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[RF,v ;flat ,* ,12] flat_store_dwordx4\t%A0, %1%O0%g0
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[v ,RF ;flat ,* ,12] flat_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\t0
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[v ,v ;vmult,* ,* ] #
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[v ,Sv ;vmult,* ,* ] #
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[SD,v ;vmult,* ,* ] #
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||||
[RM,v ;flat ,yes,12] global_store_dwordx4\t%A0, %1%O0%g0
|
||||
[v ,RM ;flat ,* ,12] global_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
[RL,v ;ds ,* ,12] ds_write_b128\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
|
||||
[v ,RL ;ds ,* ,12] ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
|
||||
}
|
||||
"reload_completed
|
||||
&& REG_P (operands[0])
|
||||
&& (REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_INT)"
|
||||
|
|
@ -695,11 +680,7 @@
|
|||
operands[3] = gcn_operand_part (TImode, operands[1], 1);
|
||||
operands[0] = gcn_operand_part (TImode, operands[0], 0);
|
||||
operands[1] = gcn_operand_part (TImode, operands[1], 0);
|
||||
}
|
||||
[(set_attr "type" "mult,smem,smem,flat,flat,vmult,vmult,vmult,flat,flat,\
|
||||
ds,ds")
|
||||
(set_attr "delayeduse" "*,*,yes,*,*,*,*,*,yes,*,*,*")
|
||||
(set_attr "length" "*,12,12,12,12,*,*,*,12,12,12,12")])
|
||||
})
|
||||
|
||||
;; }}}
|
||||
;; {{{ Prologue/Epilogue
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue