[PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction
gcc/: * config/aarch64/aarch64-builtins.c (aarch64_types_cmtst_qualifiers, TYPES_TST): Define. (aarch64_fold_builtin): Update pattern for cmtst. * config/aarch64/aarch64-protos.h (aarch64_const_vec_all_same_int_p): Declare. * config/aarch64/aarch64-simd-builtins.def (cmtst): Update qualifiers. * config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>): Switch operands, separate out more cases, refactor. (aarch64_cmtst<mode>): Rewrite pattern to match (plus ... -1). * config/aarch64.c (aarch64_const_vec_all_same_int_p): Take single argument; rename old version to... (aarch64_const_vec_all_same_in_range_p): ...this. (aarch64_print_operand, aarch64_simd_shift_imm_p): Follow renaming. * config/aarch64/predicates.md (aarch64_simd_imm_minus_one): Define. gcc/testsuite/: * gcc.target/aarch64/simd/int_comparisons.x: New file. * gcc.target/aarch64/simd/int_comparisons_1.c: New test. * gcc.target/aarch64/simd/int_comparisons_2.c: Ditto. From-SVN: r214948
This commit is contained in:
Alan Lawrence
Alan Lawrence
parent
e625e71548
commit
ddeabd3e66
11 changed files with 389 additions and 60 deletions
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@ -1,3 +1,26 @@
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2014-09-05 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-builtins.c (aarch64_types_cmtst_qualifiers,
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TYPES_TST): Define.
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(aarch64_fold_builtin): Update pattern for cmtst.
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* config/aarch64/aarch64-protos.h (aarch64_const_vec_all_same_int_p):
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Declare.
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* config/aarch64/aarch64-simd-builtins.def (cmtst): Update qualifiers.
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* config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>):
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Switch operands, separate out more cases, refactor.
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(aarch64_cmtst<mode>): Rewrite pattern to match (plus ... -1).
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* config/aarch64.c (aarch64_const_vec_all_same_int_p): Take single
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argument; rename old version to...
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(aarch64_const_vec_all_same_in_range_p): ...this.
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(aarch64_print_operand, aarch64_simd_shift_imm_p): Follow renaming.
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* config/aarch64/predicates.md (aarch64_simd_imm_minus_one): Define.
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2014-09-05 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
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@ -144,6 +144,11 @@ aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_maybe_immediate };
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#define TYPES_BINOP (aarch64_types_binop_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_cmtst_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_none,
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qualifier_internal, qualifier_internal };
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#define TYPES_TST (aarch64_types_cmtst_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_binopv_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_void, qualifier_none, qualifier_none };
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#define TYPES_BINOPV (aarch64_types_binopv_qualifiers)
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@ -1285,7 +1290,7 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
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BUILTIN_VALLDI (BINOP, cmeq, 0)
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return fold_build2 (EQ_EXPR, type, args[0], args[1]);
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break;
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BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
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BUILTIN_VSDQ_I_DI (TST, cmtst, 0)
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{
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tree and_node = fold_build2 (BIT_AND_EXPR, type, args[0], args[1]);
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tree vec_zero_node = build_zero_cst (type);
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@ -180,6 +180,7 @@ bool aarch64_cannot_change_mode_class (enum machine_mode,
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enum reg_class);
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enum aarch64_symbol_type
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aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context);
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bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
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bool aarch64_constant_address_p (rtx);
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bool aarch64_expand_movmem (rtx *);
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bool aarch64_float_const_zero_rtx_p (rtx);
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@ -246,7 +246,7 @@
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/* Implemented by aarch64_cm<cmp><mode>. */
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BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
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BUILTIN_VSDQ_I_DI (TST, cmtst, 0)
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/* Implemented by reduc_<sur>plus_<mode>. */
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BUILTIN_VALL (UNOP, reduc_splus_, 10)
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@ -1912,58 +1912,94 @@
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(match_operand:VDQ 2 "nonmemory_operand")))]
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"TARGET_SIMD"
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{
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int inverse = 0, has_zero_imm_form = 0;
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rtx op1 = operands[1];
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rtx op2 = operands[2];
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rtx mask = gen_reg_rtx (<MODE>mode);
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enum rtx_code code = GET_CODE (operands[3]);
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switch (GET_CODE (operands[3]))
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/* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
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and desirable for other comparisons if it results in FOO ? -1 : 0
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(this allows direct use of the comparison result without a bsl). */
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if (code == NE
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|| (code != EQ
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&& op1 == CONST0_RTX (<V_cmp_result>mode)
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&& op2 == CONSTM1_RTX (<V_cmp_result>mode)))
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{
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op1 = operands[2];
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op2 = operands[1];
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switch (code)
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{
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case LE: code = GT; break;
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case LT: code = GE; break;
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case GE: code = LT; break;
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case GT: code = LE; break;
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/* No case EQ. */
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case NE: code = EQ; break;
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case LTU: code = GEU; break;
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case LEU: code = GTU; break;
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case GTU: code = LEU; break;
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case GEU: code = LTU; break;
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default: gcc_unreachable ();
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}
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}
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/* Make sure we can handle the last operand. */
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switch (code)
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{
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case NE:
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/* Normalized to EQ above. */
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gcc_unreachable ();
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case LE:
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case LT:
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case NE:
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inverse = 1;
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/* Fall through. */
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case GE:
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case GT:
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case EQ:
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has_zero_imm_form = 1;
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break;
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case LEU:
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case LTU:
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inverse = 1;
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break;
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/* These instructions have a form taking an immediate zero. */
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if (operands[5] == CONST0_RTX (<MODE>mode))
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break;
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/* Fall through, as may need to load into register. */
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default:
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if (!REG_P (operands[5]))
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operands[5] = force_reg (<MODE>mode, operands[5]);
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break;
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}
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if (!REG_P (operands[5])
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&& (operands[5] != CONST0_RTX (<MODE>mode) || !has_zero_imm_form))
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operands[5] = force_reg (<MODE>mode, operands[5]);
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switch (GET_CODE (operands[3]))
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switch (code)
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{
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case LT:
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emit_insn (gen_aarch64_cmlt<mode> (mask, operands[4], operands[5]));
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break;
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case GE:
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emit_insn (gen_aarch64_cmge<mode> (mask, operands[4], operands[5]));
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break;
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case LE:
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emit_insn (gen_aarch64_cmle<mode> (mask, operands[4], operands[5]));
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break;
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case GT:
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emit_insn (gen_aarch64_cmgt<mode> (mask, operands[4], operands[5]));
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break;
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case LTU:
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emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[5], operands[4]));
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break;
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case GEU:
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emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));
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break;
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case LEU:
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emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[5], operands[4]));
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break;
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case GTU:
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emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));
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break;
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case NE:
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/* NE has been normalized to EQ above. */
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case EQ:
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emit_insn (gen_aarch64_cmeq<mode> (mask, operands[4], operands[5]));
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break;
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@ -1972,12 +2008,6 @@
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gcc_unreachable ();
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}
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if (inverse)
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{
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op1 = operands[2];
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op2 = operands[1];
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}
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/* If we have (a = (b CMP c) ? -1 : 0);
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Then we can simply move the generated mask. */
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@ -3932,14 +3962,22 @@
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;; cmtst
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;; Although neg (ne (and x y) 0) is the natural way of expressing a cmtst,
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;; we don't have any insns using ne, and aarch64_vcond_internal outputs
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;; not (neg (eq (and x y) 0))
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;; which is rewritten by simplify_rtx as
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;; plus (eq (and x y) 0) -1.
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(define_insn "aarch64_cmtst<mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
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(neg:<V_cmp_result>
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(ne:<V_cmp_result>
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(plus:<V_cmp_result>
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(eq:<V_cmp_result>
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(and:VDQ
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(match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w"))
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(vec_duplicate:<V_cmp_result> (const_int 0)))))]
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(match_operand:VDQ 3 "aarch64_simd_imm_zero"))
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(match_operand:<V_cmp_result> 4 "aarch64_simd_imm_minus_one")))
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]
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"TARGET_SIMD"
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"cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
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[(set_attr "type" "neon_tst<q>")]
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@ -137,9 +137,6 @@ static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
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static void aarch64_override_options_after_change (void);
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static bool aarch64_vector_mode_supported_p (enum machine_mode);
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static unsigned bit_count (unsigned HOST_WIDE_INT);
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static bool aarch64_const_vec_all_same_int_p (rtx,
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HOST_WIDE_INT, HOST_WIDE_INT);
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static bool aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
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const unsigned char *sel);
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static int aarch64_address_cost (rtx, enum machine_mode, addr_space_t, bool);
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@ -3576,6 +3573,36 @@ aarch64_get_condition_code (rtx x)
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}
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}
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bool
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aarch64_const_vec_all_same_in_range_p (rtx x,
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HOST_WIDE_INT minval,
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HOST_WIDE_INT maxval)
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{
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HOST_WIDE_INT firstval;
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int count, i;
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if (GET_CODE (x) != CONST_VECTOR
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|| GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT)
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return false;
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firstval = INTVAL (CONST_VECTOR_ELT (x, 0));
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if (firstval < minval || firstval > maxval)
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return false;
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count = CONST_VECTOR_NUNITS (x);
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for (i = 1; i < count; i++)
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if (INTVAL (CONST_VECTOR_ELT (x, i)) != firstval)
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return false;
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return true;
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}
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bool
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aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)
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{
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return aarch64_const_vec_all_same_in_range_p (x, val, val);
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}
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static unsigned
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bit_count (unsigned HOST_WIDE_INT value)
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{
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@ -3827,9 +3854,10 @@ aarch64_print_operand (FILE *f, rtx x, char code)
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case CONST_VECTOR:
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if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_INT)
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{
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gcc_assert (aarch64_const_vec_all_same_int_p (x,
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HOST_WIDE_INT_MIN,
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HOST_WIDE_INT_MAX));
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gcc_assert (
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aarch64_const_vec_all_same_in_range_p (x,
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HOST_WIDE_INT_MIN,
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HOST_WIDE_INT_MAX));
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asm_fprintf (f, "%wd", INTVAL (CONST_VECTOR_ELT (x, 0)));
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}
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else if (aarch64_simd_imm_zero_p (x, GET_MODE (x)))
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@ -7732,39 +7760,15 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse,
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#undef CHECK
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}
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static bool
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aarch64_const_vec_all_same_int_p (rtx x,
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HOST_WIDE_INT minval,
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HOST_WIDE_INT maxval)
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{
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HOST_WIDE_INT firstval;
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int count, i;
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if (GET_CODE (x) != CONST_VECTOR
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|| GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT)
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return false;
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firstval = INTVAL (CONST_VECTOR_ELT (x, 0));
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if (firstval < minval || firstval > maxval)
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return false;
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count = CONST_VECTOR_NUNITS (x);
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for (i = 1; i < count; i++)
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if (INTVAL (CONST_VECTOR_ELT (x, i)) != firstval)
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return false;
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return true;
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}
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/* Check of immediate shift constants are within range. */
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bool
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aarch64_simd_shift_imm_p (rtx x, enum machine_mode mode, bool left)
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{
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int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT;
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if (left)
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return aarch64_const_vec_all_same_int_p (x, 0, bit_width - 1);
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return aarch64_const_vec_all_same_in_range_p (x, 0, bit_width - 1);
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else
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return aarch64_const_vec_all_same_int_p (x, 1, bit_width);
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return aarch64_const_vec_all_same_in_range_p (x, 1, bit_width);
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}
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/* Return true if X is a uniform vector where all elements
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@ -273,3 +273,9 @@
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{
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return aarch64_simd_imm_zero_p (op, mode);
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})
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(define_special_predicate "aarch64_simd_imm_minus_one"
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(match_code "const_vector")
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{
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return aarch64_const_vec_all_same_int_p (op, -1);
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})
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@ -1,3 +1,9 @@
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2014-09-05 Alan Lawrence <alan.lawrence@arm.com>
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* gcc.target/aarch64/simd/int_comparisons.x: New file.
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* gcc.target/aarch64/simd/int_comparisons_1.c: New test.
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* gcc.target/aarch64/simd/int_comparisons_2.c: Ditto.
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2014-09-05 Alan Lawrence <alan.lawrence@arm.com>
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* gcc.target/aarch64/simd/vrbit_1.c: New test.
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68
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons.x
Normal file
68
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons.x
Normal file
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@ -0,0 +1,68 @@
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/* test_vcXXX wrappers for all the vcXXX (vector compare) and vtst intrinsics
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in arm_neon.h (excluding the 64x1 variants as these generally produce scalar
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not vector ops). */
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#include "arm_neon.h"
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#define DONT_FORCE(X)
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#define FORCE_SIMD(V1) asm volatile ("mov %d0, %1.d[0]" \
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: "=w"(V1) \
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: "w"(V1) \
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: /* No clobbers */);
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#define OP1(SIZE, OP, BASETYPE, SUFFIX, FORCE) uint##SIZE##_t \
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test_v##OP##SUFFIX (BASETYPE##SIZE##_t a) \
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{ \
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uint##SIZE##_t res; \
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FORCE (a); \
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res = v##OP##SUFFIX (a); \
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FORCE (res); \
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return res; \
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}
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#define OP2(SIZE, OP, BASETYPE, SUFFIX, FORCE) uint##SIZE##_t \
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test_v##OP##SUFFIX (BASETYPE##SIZE##_t a, BASETYPE##SIZE##_t b) \
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{ \
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uint##SIZE##_t res; \
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FORCE (a); \
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FORCE (b); \
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res = v##OP##SUFFIX (a, b); \
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FORCE (res); \
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return res; \
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}
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#define UNSIGNED_OPS(SIZE, BASETYPE, SUFFIX, FORCE) \
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OP2 (SIZE, tst, BASETYPE, SUFFIX, FORCE) \
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OP1 (SIZE, ceqz, BASETYPE, SUFFIX, FORCE) \
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OP2 (SIZE, ceq, BASETYPE, SUFFIX, FORCE) \
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OP2 (SIZE, cge, BASETYPE, SUFFIX, FORCE) \
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OP2 (SIZE, cgt, BASETYPE, SUFFIX, FORCE) \
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OP2 (SIZE, cle, BASETYPE, SUFFIX, FORCE) \
|
||||
OP2 (SIZE, clt, BASETYPE, SUFFIX, FORCE)
|
||||
|
||||
#define ALL_OPS(SIZE, BASETYPE, SUFFIX, FORCE) \
|
||||
OP1 (SIZE, cgez, BASETYPE, SUFFIX, FORCE) \
|
||||
OP1 (SIZE, cgtz, BASETYPE, SUFFIX, FORCE) \
|
||||
OP1 (SIZE, clez, BASETYPE, SUFFIX, FORCE) \
|
||||
OP1 (SIZE, cltz, BASETYPE, SUFFIX, FORCE) \
|
||||
UNSIGNED_OPS (SIZE, BASETYPE, SUFFIX, FORCE)
|
||||
|
||||
ALL_OPS (8x8, int, _s8, DONT_FORCE)
|
||||
ALL_OPS (16x4, int, _s16, DONT_FORCE)
|
||||
ALL_OPS (32x2, int, _s32, DONT_FORCE)
|
||||
ALL_OPS (64x1, int, _s64, DONT_FORCE)
|
||||
ALL_OPS (64, int, d_s64, FORCE_SIMD)
|
||||
ALL_OPS (8x16, int, q_s8, DONT_FORCE)
|
||||
ALL_OPS (16x8, int, q_s16, DONT_FORCE)
|
||||
ALL_OPS (32x4, int, q_s32, DONT_FORCE)
|
||||
ALL_OPS (64x2, int, q_s64, DONT_FORCE)
|
||||
UNSIGNED_OPS (8x8, uint, _u8, DONT_FORCE)
|
||||
UNSIGNED_OPS (16x4, uint, _u16, DONT_FORCE)
|
||||
UNSIGNED_OPS (32x2, uint, _u32, DONT_FORCE)
|
||||
UNSIGNED_OPS (64x1, uint, _u64, DONT_FORCE)
|
||||
UNSIGNED_OPS (64, uint, d_u64, FORCE_SIMD)
|
||||
UNSIGNED_OPS (8x16, uint, q_u8, DONT_FORCE)
|
||||
UNSIGNED_OPS (16x8, uint, q_u16, DONT_FORCE)
|
||||
UNSIGNED_OPS (32x4, uint, q_u32, DONT_FORCE)
|
||||
UNSIGNED_OPS (64x2, uint, q_u64, DONT_FORCE)
|
||||
|
||||
47
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_1.c
Normal file
47
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_1.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O3 -fno-inline" } */
|
||||
|
||||
/* Scan-assembler test, so, incorporate as little other code as possible. */
|
||||
|
||||
#include "arm_neon.h"
|
||||
#include "int_comparisons.x"
|
||||
|
||||
/* Operations on all 18 integer types: (q?)_[su](8|16|32|64), d_[su]64.
|
||||
(d?)_[us]64 generate regs of form 'd0' rather than e.g. 'v0.2d'. */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmeq\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmtst\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmtst\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
|
||||
/* vcge + vcle both implemented with cmge (signed) or cmhs (unsigned). */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmhs\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmhs\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
|
||||
/* vcgt + vclt both implemented with cmgt (signed) or cmhi (unsigned). */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmhi\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\]" 14 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmhi\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]+d\[0-9\]+" 4 } } */
|
||||
|
||||
/* Comparisons against immediate zero, on the 8 signed integer types only. */
|
||||
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
|
||||
/* For int64_t and int64x1_t, combine_simplify_rtx failure of
|
||||
https://gcc.gnu.org/ml/gcc/2014-06/msg00253.html
|
||||
prevents generation of cmge....#0, instead producing mvn + sshr. */
|
||||
/* { #dg-final { scan-assembler-times "\[ \t\]cmge\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmgt\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmle\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmle\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?0" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\]cmlt\[ \t\]+v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*v\[0-9\]+\.\[0-9\]+\[bshd\],\[ \t\]*#?0" 7 } } */
|
||||
/* For int64_t and int64x1_t, cmlt ... #0 and sshr ... #63 are equivalent,
|
||||
so allow either. cmgez issue above results in extra 2 * sshr....63. */
|
||||
/* { dg-final { scan-assembler-times "\[ \t\](?:cmlt|sshr)\[ \t\]+d\[0-9\]+,\[ \t\]*d\[0-9\]+,\[ \t\]*#?(?:0|63)" 4 } } */
|
||||
|
||||
// All should have been compiled into single insns without inverting result:
|
||||
/* { dg-final { scan-assembler-not "not" } } */
|
||||
131
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_2.c
Normal file
131
gcc/testsuite/gcc.target/aarch64/simd/int_comparisons_2.c
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O2 -fno-inline" } */
|
||||
/* Stops the test_xxx methods being inlined into main, thus preventing constant
|
||||
propagation. */
|
||||
|
||||
#include "int_comparisons.x"
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
#define CHECK2(R0, R1) if (res[0] != R0 || res[1] != R1) abort ()
|
||||
|
||||
#define TEST2(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) { \
|
||||
BASETYPE##_t _a[2] = {2, 3}; \
|
||||
BASETYPE##x2_t a = vld1##SUFFIX (_a); \
|
||||
BASETYPE##_t _b[2] = {1, 3}; \
|
||||
BASETYPE##x2_t b = vld1##SUFFIX (_b); \
|
||||
RESTYPE res[2]; \
|
||||
vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b)); CHECK2 (0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (b, a)); CHECK2 (-1, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b)); CHECK2 (0, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (b, a)); CHECK2 (-1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b)); CHECK2 (0, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b)); CHECK2 (-1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (b, a)); CHECK2 (0, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b)); CHECK2 (-1, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (b, a)); CHECK2 (0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b)); CHECK2 (0, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a + 1, b)); CHECK2 (-1, 0); \
|
||||
}
|
||||
|
||||
#define CHECK4(T, R0, R1, R2, R3) \
|
||||
if (res[0] != (T)R0 || res[1] != (T)R1 \
|
||||
|| res[2] != (T)R2 || res[3] != (T)R3) abort ()
|
||||
|
||||
#define TEST4(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) { \
|
||||
BASETYPE##_t _a[4] = {1, 2, 3, 4}; \
|
||||
BASETYPE##x4_t a = vld1##SUFFIX (_a); \
|
||||
BASETYPE##_t _b[4] = {4, 2, 1, 3}; \
|
||||
BASETYPE##x4_t b = vld1##SUFFIX (_b); \
|
||||
RESTYPE res[4]; \
|
||||
vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, -1, 0, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, -1, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, 0, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, 0, -1, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, 0, 0, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b)); \
|
||||
CHECK4 (RESTYPE, 0, -1, -1, 0); \
|
||||
}
|
||||
|
||||
#define CHECK8(T, R0, R1, R2, R3, R4, R5, R6, R7) \
|
||||
if (res[0] != (T)R0 || res[1] != (T)R1 || res[2] != (T)R2 || res[3] != (T)R3 \
|
||||
|| res[4] != (T)R4 || res[5] != (T)R5 || res[6] != (T)R6 \
|
||||
|| res[7] != (T)R7) abort ()
|
||||
|
||||
#define TEST8(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) { \
|
||||
BASETYPE##_t _a[8] = {1, 2, 3, 4, 5, 6, 7, 8}; \
|
||||
BASETYPE##x8_t a = vld1##SUFFIX (_a); \
|
||||
BASETYPE##_t _b[8] = {4, 2, 1, 3, 2, 6, 8, 9}; \
|
||||
BASETYPE##x8_t b = vld1##SUFFIX (_b); \
|
||||
RESTYPE res[8]; \
|
||||
vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, -1, 0, 0, 0, 0, 0, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, -1, -1, 0, 0, 0, -1, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, 0, -1, 0, 0, 0, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, 0, -1, -1, -1, -1, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, 0, 0, -1, -1, -1, 0, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b)); \
|
||||
CHECK8 (RESTYPE, 0, -1, -1, 0, 0, -1, 0, -1); \
|
||||
}
|
||||
|
||||
/* 16-way tests use same 8 values twice. */
|
||||
#define CHECK16(T, R0, R1, R2, R3, R4, R5, R6, R7) \
|
||||
if (res[0] != (T)R0 || res[1] != (T)R1 || res[2] != (T)R2 || res[3] != (T)R3 \
|
||||
|| res[4] != (T)R4 || res[5] != (T)R5 || res[6] != (T)R6 \
|
||||
|| res[7] != (T)R7 || res[8] != (T)R0 || res[9] != (T)R1 \
|
||||
|| res[10] != (T)R2 || res[11] != (T)R3 || res[12] != (T)R4 \
|
||||
|| res[13] != (T)R5 || res[14] != (T)R6 || res[15] != (T)R7) abort ()
|
||||
|
||||
#define TEST16(BASETYPE, SUFFIX, RESTYPE, ST1_SUFFIX) { \
|
||||
BASETYPE##_t _a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; \
|
||||
BASETYPE##x16_t a = vld1##SUFFIX (_a); \
|
||||
BASETYPE##_t _b[16] = {4, 2, 1, 3, 2, 6, 8, 9, 4, 2, 1, 3, 2, 6, 8, 9}; \
|
||||
BASETYPE##x16_t b = vld1##SUFFIX (_b); \
|
||||
RESTYPE res[16]; \
|
||||
vst1##ST1_SUFFIX (res, test_vclt##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, -1, 0, 0, 0, 0, 0, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vcle##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, -1, -1, 0, 0, 0, -1, -1, -1); \
|
||||
vst1##ST1_SUFFIX (res, test_vceq##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, 0, -1, 0, 0, 0, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcge##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, 0, -1, -1, -1, -1, -1, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vcgt##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, 0, 0, -1, -1, -1, 0, 0, 0); \
|
||||
vst1##ST1_SUFFIX (res, test_vtst##SUFFIX (a, b)); \
|
||||
CHECK16 (RESTYPE, 0, -1, -1, 0, 0, -1, 0, -1); \
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
TEST2 (int32, _s32, uint32_t, _u32);
|
||||
TEST2 (uint32, _u32, uint32_t, _u32);
|
||||
TEST2 (int64, q_s64, uint64_t, q_u64);
|
||||
TEST2 (uint64, q_u64, uint64_t, q_u64);
|
||||
|
||||
TEST4 (int16, _s16, uint16_t, _u16);
|
||||
TEST4 (uint16, _u16, uint16_t, _u16);
|
||||
TEST4 (int32, q_s32, uint32_t, q_u32);
|
||||
TEST4 (uint32, q_u32, uint32_t, q_u32);
|
||||
|
||||
TEST8 (int8, _s8, uint8_t, _u8);
|
||||
TEST8 (uint8, _u8, uint8_t, _u8);
|
||||
TEST8 (int16, q_s16, uint16_t, q_u16);
|
||||
TEST8 (uint16, q_u16, uint16_t, q_u16);
|
||||
|
||||
TEST16 (int8, q_s8, uint8_t, q_u8);
|
||||
TEST16 (uint8, q_u8, uint8_t, q_u8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Add table
Reference in a new issue