arm.c (neon_vector_mem_operand): Handle element/structure loads.
2009-05-15 Paul Brook <paul@codesourcery.com> Sandra Loosemore <sandra@codesourcery.com> gcc/ * config/arm/arm.c (neon_vector_mem_operand): Handle element/structure loads. Allow PRE_DEC. (output_move_neon): Handle PRE_DEC. (arm_print_operand): Add 'A' for neon structure loads. * config/arm/arm-protos.h (neon_vector_mem_operand): Update prototype. * config/arm/neon.md (neon_mov): Update comment. * config/arm/constraints.md (Un, Us): Update neon_vector_mem_operand calls. (Um): New constraint. Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com> From-SVN: r147577
This commit is contained in:
Paul Brook
Sandra Loosemore
parent
1d405d7b41
commit
dc34db56f1
5 changed files with 62 additions and 21 deletions
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@ -1,3 +1,17 @@
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2009-05-15 Paul Brook <paul@codesourcery.com>
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Sandra Loosemore <sandra@codesourcery.com>
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gcc/
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* config/arm/arm.c (neon_vector_mem_operand): Handle element/structure
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loads. Allow PRE_DEC.
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(output_move_neon): Handle PRE_DEC.
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(arm_print_operand): Add 'A' for neon structure loads.
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* config/arm/arm-protos.h (neon_vector_mem_operand): Update prototype.
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* config/arm/neon.md (neon_mov): Update comment.
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* config/arm/constraints.md (Un, Us): Update neon_vector_mem_operand
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calls.
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(Um): New constraint.
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2009-05-15 Jan Hubicka <jh@suse.cz>
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Revert the following patch until testsuite fallout is fixed:
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@ -84,7 +84,7 @@ extern bool arm_cannot_force_const_mem (rtx);
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extern int cirrus_memory_offset (rtx);
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extern int arm_coproc_mem_operand (rtx, bool);
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extern int neon_vector_mem_operand (rtx, bool);
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extern int neon_vector_mem_operand (rtx, int);
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extern int neon_struct_mem_operand (rtx);
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extern int arm_no_early_store_addr_dep (rtx, rtx);
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extern int arm_no_early_alu_shift_dep (rtx, rtx);
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@ -6961,10 +6961,13 @@ arm_coproc_mem_operand (rtx op, bool wb)
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}
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/* Return TRUE if OP is a memory operand which we can load or store a vector
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to/from. If CORE is true, we're moving from ARM registers not Neon
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registers. */
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to/from. TYPE is one of the following values:
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0 - Vector load/stor (vldr)
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1 - Core registers (ldm)
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2 - Element/structure loads (vld1)
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*/
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int
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neon_vector_mem_operand (rtx op, bool core)
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neon_vector_mem_operand (rtx op, int type)
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{
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rtx ind;
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@ -6997,23 +7000,15 @@ neon_vector_mem_operand (rtx op, bool core)
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return arm_address_register_rtx_p (ind, 0);
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/* Allow post-increment with Neon registers. */
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if (!core && GET_CODE (ind) == POST_INC)
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if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC))
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return arm_address_register_rtx_p (XEXP (ind, 0), 0);
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#if 0
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/* FIXME: We can support this too if we use VLD1/VST1. */
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if (!core
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&& GET_CODE (ind) == POST_MODIFY
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&& arm_address_register_rtx_p (XEXP (ind, 0), 0)
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&& GET_CODE (XEXP (ind, 1)) == PLUS
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&& rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
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ind = XEXP (ind, 1);
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#endif
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/* FIXME: vld1 allows register post-modify. */
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/* Match:
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(plus (reg)
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(const)). */
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if (!core
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if (type == 0
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&& GET_CODE (ind) == PLUS
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&& GET_CODE (XEXP (ind, 0)) == REG
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&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
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@ -7083,7 +7078,7 @@ coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
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if (TARGET_NEON
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&& (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
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|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
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&& neon_vector_mem_operand (x, FALSE))
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&& neon_vector_mem_operand (x, 0))
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return NO_REGS;
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if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
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@ -10799,7 +10794,7 @@ output_move_double (rtx *operands)
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}
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/* Output a move, load or store for quad-word vectors in ARM registers. Only
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handles MEMs accepted by neon_vector_mem_operand with CORE=true. */
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handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
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const char *
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output_move_quad (rtx *operands)
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@ -10995,6 +10990,13 @@ output_move_neon (rtx *operands)
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ops[1] = reg;
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break;
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case PRE_DEC:
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/* FIXME: We should be using vld1/vst1 here in BE mode? */
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templ = "v%smdb%%?\t%%0!, %%h1";
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ops[0] = XEXP (addr, 0);
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ops[1] = reg;
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break;
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case POST_MODIFY:
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/* FIXME: Not currently enabled in neon_vector_mem_operand. */
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gcc_unreachable ();
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@ -13859,6 +13861,24 @@ arm_print_operand (FILE *stream, rtx x, int code)
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}
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return;
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/* Memory operand for vld1/vst1 instruction. */
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case 'A':
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{
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rtx addr;
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bool postinc = FALSE;
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gcc_assert (GET_CODE (x) == MEM);
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addr = XEXP (x, 0);
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if (GET_CODE (addr) == POST_INC)
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{
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postinc = 1;
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addr = XEXP (addr, 0);
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}
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asm_fprintf (stream, "[%r]", REGNO (addr));
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if (postinc)
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fputs("!", stream);
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}
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return;
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default:
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if (x == 0)
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{
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@ -32,7 +32,7 @@
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv
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;; The following memory constraints have been used:
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;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us
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;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
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;; in ARM state: Uq
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@ -213,18 +213,25 @@
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(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
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(define_memory_constraint "Un"
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"@internal
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In ARM/Thumb-2 state a valid address for Neon doubleword vector
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load/store instructions."
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(and (match_code "mem")
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
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(define_memory_constraint "Um"
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"@internal
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In ARM/Thumb-2 state a valid address for Neon element and structure
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load/store instructions."
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(and (match_code "mem")
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)")))
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
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(define_memory_constraint "Us"
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"@internal
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In ARM/Thumb-2 state a valid address for non-offset loads/stores of
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quad-word values in four ARM registers."
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(and (match_code "mem")
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)")))
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
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(define_memory_constraint "Uq"
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"@internal
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@ -481,7 +481,7 @@
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/* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp
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below must be changed to output_move_neon (which will use the
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element/structure loads/stores), and the constraint changed to 'Un' instead
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element/structure loads/stores), and the constraint changed to 'Um' instead
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of 'Uv'. */
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switch (which_alternative)
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