Revert LRA SPARC changes for now.
gcc/ PR/67622 Revert: 2015-09-11 David S. Miller <davem@davemloft.net> * config/sparc/constraints.md: Make "U" constraint a real register constraint. * config/sparc/sparc.c (TARGET_LRA_P): Define. (D_MODES, DF_MODES): Add missing cast. (TF_MODES, TF_MODES_NO_S): Include T_MODE. (OF_MODES, OF_MODES_NO_S): Include O_MODE. (sparc_register_move_cost): Decrease Niagara/UltrsSPARC memory cost to 8. * config/sparc/sparc.h (PROMOTE_MODE): Define. * config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not provide these insn when flag_pic. 2015-09-17 David S. Miller <davem@davemloft.net> * config/sparc/sparc-protos.h (sparc_secondary_memory_needed): Declare. * config/sparc/sparc.c (sparc_secondary_memory_needed): New function. * config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): Use it. (HARD_REGNO_CALLER_SAVE_MODE): Define. * config/sparc/sparc.md (sethi_di_medlow, losum_di_medlow, seth44) (setm44, setl44, sethh, setlm, sethm, setlo, embmedany_sethi) (embmedany_losum, embmedany_brsum, embmedany_textuhi) (embmedany_texthi, embmedany_textulo, embmedany_textlo): Do not provide when flag_pic. From-SVN: r227993
This commit is contained in:
David S. Miller
David S. Miller
parent
36d0586f56
commit
dc2a24eddf
6 changed files with 107 additions and 74 deletions
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@ -1,3 +1,35 @@
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2015-09-21 David S. Miller <davem@davemloft.net>
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PR/67622
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Revert:
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2015-09-11 David S. Miller <davem@davemloft.net>
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* config/sparc/constraints.md: Make "U" constraint a real register
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constraint.
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* config/sparc/sparc.c (TARGET_LRA_P): Define.
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(D_MODES, DF_MODES): Add missing cast.
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(TF_MODES, TF_MODES_NO_S): Include T_MODE.
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(OF_MODES, OF_MODES_NO_S): Include O_MODE.
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(sparc_register_move_cost): Decrease Niagara/UltrsSPARC memory
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cost to 8.
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* config/sparc/sparc.h (PROMOTE_MODE): Define.
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* config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not
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provide these insn when flag_pic.
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2015-09-17 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc-protos.h (sparc_secondary_memory_needed):
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Declare.
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* config/sparc/sparc.c (sparc_secondary_memory_needed): New
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function.
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* config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): Use it.
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(HARD_REGNO_CALLER_SAVE_MODE): Define.
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* config/sparc/sparc.md (sethi_di_medlow, losum_di_medlow, seth44)
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(setm44, setl44, sethh, setlm, sethm, setlo, embmedany_sethi)
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(embmedany_losum, embmedany_brsum, embmedany_textuhi)
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(embmedany_texthi, embmedany_textulo, embmedany_textlo): Do not
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provide when flag_pic.
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2015-09-21 Jeff Law <law@redhat.com>
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* config/h8300/h8300.md (andsi3_ashift_n_lower): Avoid undefined
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@ -44,8 +44,6 @@
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(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
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"64-bit global or out register in V8+ mode")
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(define_register_constraint "U" "(TARGET_ARCH32 ? GENERAL_REGS : NO_REGS)")
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;; Floating-point constant constraints
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(define_constraint "G"
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@ -137,6 +135,51 @@
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(match_code "mem")
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(match_test "memory_ok_for_ldd (op)")))
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;; This awkward register constraint is necessary because it is not
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;; possible to express the "must be even numbered register" condition
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;; using register classes. The problem is that membership in a
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;; register class requires that all registers of a multi-regno
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;; register be included in the set. It is add_to_hard_reg_set
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;; and in_hard_reg_set_p which populate and test regsets with these
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;; semantics.
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;;
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;; So this means that we would have to put both the even and odd
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;; register into the register class, which would not restrict things
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;; at all.
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;;
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;; Using a combination of GENERAL_REGS and HARD_REGNO_MODE_OK is not a
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;; full solution either. In fact, even though IRA uses the macro
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;; HARD_REGNO_MODE_OK to calculate which registers are prohibited from
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;; use in certain modes, it still can allocate an odd hard register
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;; for DImode values. This is due to how IRA populates the table
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;; ira_useful_class_mode_regs[][]. It suffers from the same problem
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;; as using a register class to describe this restriction. Namely, it
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;; sets both the odd and even part of an even register pair in the
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;; regset. Therefore IRA can and will allocate odd registers for
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;; DImode values on 32-bit.
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;;
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;; There are legitimate cases where DImode values can end up in odd
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;; hard registers, the most notable example is argument passing.
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;;
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;; What saves us is reload and the DImode splitters. Both are
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;; necessary. The odd register splitters cannot match if, for
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;; example, we have a non-offsetable MEM. Reload will notice this
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;; case and reload the address into a single hard register.
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;;
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;; The real downfall of this awkward register constraint is that it does
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;; not evaluate to a true register class like a bonafide use of
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;; define_register_constraint would. This currently means that we cannot
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;; use LRA on Sparc, since the constraint processing of LRA really depends
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;; upon whether an extra constraint is for registers or not. It uses
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;; reg_class_for_constraint, and checks it against NO_REGS.
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(define_constraint "U"
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"Pseudo-register or hard even-numbered integer register"
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(and (match_test "TARGET_ARCH32")
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(match_code "reg")
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(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
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(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
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(match_test "register_ok_for_ldd (op)")))
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;; Equivalent to 'T' but available in 64-bit mode
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(define_memory_constraint "W"
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"Memory reference for 'e' constraint floating-point register"
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@ -62,8 +62,6 @@ extern bool constant_address_p (rtx);
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extern bool legitimate_pic_operand_p (rtx);
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extern rtx sparc_legitimize_reload_address (rtx, machine_mode, int, int,
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int, int *win);
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extern bool sparc_secondary_memory_needed (enum reg_class, enum reg_class,
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machine_mode);
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extern void load_got_register (void);
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extern void sparc_emit_call_insn (rtx, rtx);
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extern void sparc_defer_case_vector (rtx, rtx, int);
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@ -808,9 +808,6 @@ char sparc_hard_reg_printed[8];
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#undef TARGET_CAN_ELIMINATE
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#define TARGET_CAN_ELIMINATE sparc_can_eliminate
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#undef TARGET_LRA_P
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#define TARGET_LRA_P hook_bool_void_true
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#undef TARGET_PREFERRED_RELOAD_CLASS
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#define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
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@ -4694,7 +4691,7 @@ enum sparc_mode_class {
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((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
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/* Modes for double-word and smaller quantities. */
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#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
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#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
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/* Modes for quad-word and smaller quantities. */
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#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
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@ -4706,24 +4703,22 @@ enum sparc_mode_class {
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#define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
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/* Modes for double-float and smaller quantities. */
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#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
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#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
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/* Modes for quad-float and smaller quantities. */
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#define TF_MODES (DF_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
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#define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
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/* Modes for quad-float pairs and smaller quantities. */
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#define OF_MODES (TF_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
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#define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
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/* Modes for double-float only quantities. */
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#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
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/* Modes for quad-float and double-float only quantities. */
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#define TF_MODES_NO_S \
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(DF_MODES_NO_S | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
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#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
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/* Modes for quad-float pairs and double-float only quantities. */
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#define OF_MODES_NO_S \
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(TF_MODES_NO_S | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
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#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
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/* Modes for condition codes. */
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#define CC_MODES (1 << (int) CC_MODE)
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@ -11193,7 +11188,7 @@ sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
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|| sparc_cpu == PROCESSOR_NIAGARA2
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|| sparc_cpu == PROCESSOR_NIAGARA3
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|| sparc_cpu == PROCESSOR_NIAGARA4)
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return 8;
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return 12;
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return 6;
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}
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@ -12283,26 +12278,6 @@ sparc_expand_vector_init (rtx target, rtx vals)
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emit_move_insn (target, mem);
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}
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bool sparc_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
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machine_mode mode)
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{
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if (FP_REG_CLASS_P (class1) != FP_REG_CLASS_P (class2))
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{
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if (! TARGET_VIS3
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|| GET_MODE_SIZE (mode) > 8
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|| GET_MODE_SIZE (mode) < 4)
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return true;
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return false;
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}
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if (GET_MODE_SIZE (mode) == 4
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&& ((class1 == FP_REGS && class2 == EXTRA_FP_REGS)
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|| (class1 == EXTRA_FP_REGS && class2 == FP_REGS)))
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return true;
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return false;
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}
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/* Implement TARGET_SECONDARY_RELOAD. */
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static reg_class_t
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@ -452,17 +452,6 @@ extern enum cmodel sparc_cmodel;
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/* target machine storage layout */
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/* Define this macro if it is advisable to hold scalars in registers
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in a wider mode than that declared by the program. In such cases,
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the value is constrained to be within the bounds of the declared
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type, but kept valid in the wider mode. The signedness of the
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extension may differ from that of the type. */
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#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
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if (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < (TARGET_ARCH64 ? 8 : 4)) \
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(MODE) = TARGET_ARCH64 ? DImode : SImode;
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/* Define this if most significant bit is lowest numbered
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in instructions that operate on numbered bit-fields. */
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#define BITS_BIG_ENDIAN 1
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@ -747,12 +736,6 @@ extern int sparc_mode_class[];
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register window instruction in the prologue. */
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#define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
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/* Select a register mode required for caller save of hard regno REGNO. */
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#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
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(((MODE) == VOIDmode) ? \
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choose_hard_reg_mode ((REGNO), (NREGS), false) : \
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(MODE))
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#define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2)
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/* Specify the registers used for certain standard purposes.
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@ -1050,10 +1033,12 @@ extern char leaf_reg_remap[];
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(SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
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/* On SPARC when not VIS3 it is not possible to directly move data
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between GENERAL_REGS and FP_REGS. We also cannot move 4-byte values
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between FP_REGS and EXTRA_FP_REGS. */
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between GENERAL_REGS and FP_REGS. */
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#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
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sparc_secondary_memory_needed (CLASS1, CLASS2, MODE)
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((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \
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&& (! TARGET_VIS3 \
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|| GET_MODE_SIZE (MODE) > 8 \
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|| GET_MODE_SIZE (MODE) < 4))
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/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
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because the movsi and movsf patterns don't handle r/f moves.
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@ -1467,13 +1467,13 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "immediate_operand" "in")))]
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"! flag_pic"
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""
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"or\t%1, %%lo(%a2), %0")
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(define_insn "*movsi_high"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(high:SI (match_operand:SI 1 "immediate_operand" "in")))]
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"! flag_pic"
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""
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"sethi\t%%hi(%a1), %0")
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;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
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@ -1745,105 +1745,105 @@
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(define_insn "*sethi_di_medlow"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (match_operand:DI 1 "symbolic_operand" "")))]
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"TARGET_CM_MEDLOW && !flag_pic"
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"TARGET_CM_MEDLOW && check_pic (1)"
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"sethi\t%%hi(%a1), %0")
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(define_insn "*losum_di_medlow"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "symbolic_operand" "")))]
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"TARGET_CM_MEDLOW && !flag_pic"
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"TARGET_CM_MEDLOW"
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"or\t%1, %%lo(%a2), %0")
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(define_insn "seth44"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
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"TARGET_CM_MEDMID && !flag_pic"
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"TARGET_CM_MEDMID"
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"sethi\t%%h44(%a1), %0")
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(define_insn "setm44"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
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"TARGET_CM_MEDMID && !flag_pic"
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"TARGET_CM_MEDMID"
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"or\t%1, %%m44(%a2), %0")
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(define_insn "setl44"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "symbolic_operand" "")))]
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"TARGET_CM_MEDMID && !flag_pic"
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"TARGET_CM_MEDMID"
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"or\t%1, %%l44(%a2), %0")
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(define_insn "sethh"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
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"TARGET_CM_MEDANY && !flag_pic"
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"TARGET_CM_MEDANY"
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"sethi\t%%hh(%a1), %0")
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(define_insn "setlm"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
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"TARGET_CM_MEDANY && !flag_pic"
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"TARGET_CM_MEDANY"
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"sethi\t%%lm(%a1), %0")
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(define_insn "sethm"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
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"TARGET_CM_MEDANY && !flag_pic"
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"TARGET_CM_MEDANY"
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"or\t%1, %%hm(%a2), %0")
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(define_insn "setlo"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "symbolic_operand" "")))]
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"TARGET_CM_MEDANY && !flag_pic"
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"TARGET_CM_MEDANY"
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"or\t%1, %%lo(%a2), %0")
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(define_insn "embmedany_sethi"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
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"TARGET_CM_EMBMEDANY && !flag_pic"
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"TARGET_CM_EMBMEDANY && check_pic (1)"
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"sethi\t%%hi(%a1), %0")
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(define_insn "embmedany_losum"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "data_segment_operand" "")))]
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"TARGET_CM_EMBMEDANY && !flag_pic"
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"TARGET_CM_EMBMEDANY"
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"add\t%1, %%lo(%a2), %0")
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(define_insn "embmedany_brsum"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
|
||||
"TARGET_CM_EMBMEDANY && !flag_pic"
|
||||
"TARGET_CM_EMBMEDANY"
|
||||
"add\t%1, %_, %0")
|
||||
|
||||
(define_insn "embmedany_textuhi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
|
||||
"TARGET_CM_EMBMEDANY && !flag_pic"
|
||||
"TARGET_CM_EMBMEDANY && check_pic (1)"
|
||||
"sethi\t%%uhi(%a1), %0")
|
||||
|
||||
(define_insn "embmedany_texthi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
|
||||
"TARGET_CM_EMBMEDANY && !flag_pic"
|
||||
"TARGET_CM_EMBMEDANY && check_pic (1)"
|
||||
"sethi\t%%hi(%a1), %0")
|
||||
|
||||
(define_insn "embmedany_textulo"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
|
||||
"TARGET_CM_EMBMEDANY && !flag_pic"
|
||||
"TARGET_CM_EMBMEDANY"
|
||||
"or\t%1, %%ulo(%a2), %0")
|
||||
|
||||
(define_insn "embmedany_textlo"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
|
||||
(match_operand:DI 2 "text_segment_operand" "")))]
|
||||
"TARGET_CM_EMBMEDANY && !flag_pic"
|
||||
"TARGET_CM_EMBMEDANY"
|
||||
"or\t%1, %%lo(%a2), %0")
|
||||
|
||||
;; Now some patterns to help reload out a bit.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue