sse.md (vec_extract_lo_<mode><mask_name>): Add (=v, v) alternative and explicit "memory" attribute.
* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Add (=v, v) alternative and explicit "memory" attribute. (vec_extract_lo_<mode><mask_name>): Likewise. Also add "type", "prefix", "prefix_extra", "length_immediate" and "mode" attributes. (vec_extract_lo_<mode><mask_name>): Add (=v, v) alternative and use "sselog1" type instead of "sselog". (vec_extract_hi_<mode><mask_name>): Use "sselog1" type instead of "sselog". Remove explicit "memory" attribute. (vec_extract_lo_v32hi): Add (=v, v) alternative and explicit "memory", "type", "prefix", "prefix_extra", "length_immediate" and "mode" attributes. (vec_extract_hi_v32hi): Merge all alternatives into one, use "sselog1" type instead of "sselog". Remove explicit "memory" attribute. (vec_extract_hi_v16hi): Merge each pair of alternatives into one, use "sselog1" type instead of "sselog". Remove explicit "memory" attribute. (vec_extract_lo_v64qi): Add (=v, v) alternative and explicit "memory", "type", "prefix", "prefix_extra", "length_immediate" and "mode" attributes. (vec_extract_hi_v64qi): Merge all alternatives into one, use "sselog1" type instead of "sselog". Remove explicit "memory" attribute. (vec_extract_hi_v32qi): Merge each pair of alternatives into one, use "sselog1" type instead of "sselog". Remove explicit "memory" attribute. From-SVN: r259438
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
fcab9fce57
commit
db051c243c
2 changed files with 79 additions and 43 deletions
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@ -1,5 +1,33 @@
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2018-04-17 Jakub Jelinek <jakub@redhat.com>
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* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Add
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(=v, v) alternative and explicit "memory" attribute.
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(vec_extract_lo_<mode><mask_name>): Likewise. Also add
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"type", "prefix", "prefix_extra", "length_immediate" and "mode"
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attributes.
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(vec_extract_lo_<mode><mask_name>): Add (=v, v) alternative and use
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"sselog1" type instead of "sselog".
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(vec_extract_hi_<mode><mask_name>): Use "sselog1" type instead of
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"sselog". Remove explicit "memory" attribute.
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(vec_extract_lo_v32hi): Add (=v, v) alternative and explicit "memory",
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"type", "prefix", "prefix_extra", "length_immediate" and "mode"
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attributes.
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(vec_extract_hi_v32hi): Merge all alternatives into one, use
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"sselog1" type instead of "sselog". Remove explicit "memory"
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attribute.
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(vec_extract_hi_v16hi): Merge each pair of alternatives into one,
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use "sselog1" type instead of "sselog". Remove explicit "memory"
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attribute.
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(vec_extract_lo_v64qi): Add (=v, v) alternative and explicit "memory",
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"type", "prefix", "prefix_extra", "length_immediate" and "mode"
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attributes.
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(vec_extract_hi_v64qi): Merge all alternatives into one, use
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"sselog1" type instead of "sselog". Remove explicit "memory"
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attribute.
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(vec_extract_hi_v32qi): Merge each pair of alternatives into one,
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use "sselog1" type instead of "sselog". Remove explicit "memory"
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attribute.
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PR target/85430
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* config/i386/i386.md (*ashlqi3_1_slp): Use alu1 type instead of alu.
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@ -7495,9 +7495,9 @@
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "vec_extract_lo_<mode><mask_name>"
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[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v")
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[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,<store_mask_constraint>,v")
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(vec_select:<ssehalfvecmode>
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(match_operand:V8FI 1 "<store_mask_predicate>" "v,<store_mask_constraint>")
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(match_operand:V8FI 1 "<store_mask_predicate>" "v,v,<store_mask_constraint>")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)])))]
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"TARGET_AVX512F
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@ -7511,6 +7511,7 @@
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,store,load")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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@ -7651,10 +7652,10 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m")
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[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
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(vec_select:<ssehalfvecmode>
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(match_operand:V16FI 1 "<store_mask_predicate>"
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"<store_mask_constraint>,v")
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"v,<store_mask_constraint>,v")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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@ -7670,7 +7671,13 @@
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return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
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else
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return "#";
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})
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}
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,load,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_split
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[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
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@ -7697,10 +7704,10 @@
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})
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(define_insn "vec_extract_lo_<mode><mask_name>"
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[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,m")
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[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
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(vec_select:<ssehalfvecmode>
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(match_operand:VI8F_256 1 "<store_mask_predicate>"
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"<store_mask_constraint>,v")
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"v,<store_mask_constraint>,v")
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(parallel [(const_int 0) (const_int 1)])))]
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"TARGET_AVX
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&& <mask_avx512vl_condition> && <mask_avx512dq_condition>
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@ -7711,10 +7718,10 @@
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else
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return "#";
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}
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,store")
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(set_attr "memory" "none,load,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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@ -7745,10 +7752,9 @@
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else
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return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
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}
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,store")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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@ -7854,9 +7860,9 @@
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn_and_split "vec_extract_lo_v32hi"
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,m")
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,v,m")
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(vec_select:V16HI
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(match_operand:V32HI 1 "nonimmediate_operand" "vm,v")
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(match_operand:V32HI 1 "nonimmediate_operand" "v,m,v")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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@ -7886,12 +7892,18 @@
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operands[0] = lowpart_subreg (V32HImode, operands[0], V16HImode);
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else
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operands[1] = gen_lowpart (V16HImode, operands[1]);
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})
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}
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,load,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "vec_extract_hi_v32hi"
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,m")
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=vm")
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(vec_select:V16HI
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(match_operand:V32HI 1 "register_operand" "v,v")
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(match_operand:V32HI 1 "register_operand" "v")
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(parallel [(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 20) (const_int 21)
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@ -7902,10 +7914,9 @@
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(const_int 30) (const_int 31)])))]
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"TARGET_AVX512F"
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"vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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@ -7924,33 +7935,29 @@
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"operands[1] = gen_lowpart (V8HImode, operands[1]);")
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(define_insn "vec_extract_hi_v16hi"
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[(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m,v,m,v,m")
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[(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm,vm,vm")
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(vec_select:V8HI
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(match_operand:V16HI 1 "register_operand" "x,x,v,v,v,v")
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(match_operand:V16HI 1 "register_operand" "x,v,v")
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(parallel [(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)])))]
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"TARGET_AVX"
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"@
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vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
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vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}
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vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}"
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "isa" "*,*,avx512dq,avx512dq,avx512f,avx512f")
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(set_attr "memory" "none,store,none,store,none,store")
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(set_attr "prefix" "vex,vex,evex,evex,evex,evex")
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(set_attr "isa" "*,avx512dq,avx512f")
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(set_attr "prefix" "vex,evex,evex")
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(set_attr "mode" "OI")])
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(define_insn_and_split "vec_extract_lo_v64qi"
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[(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m")
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[(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,v,m")
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(vec_select:V32QI
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(match_operand:V64QI 1 "nonimmediate_operand" "vm,v")
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(match_operand:V64QI 1 "nonimmediate_operand" "v,m,v")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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@ -7988,12 +7995,18 @@
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operands[0] = lowpart_subreg (V64QImode, operands[0], V32QImode);
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else
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operands[1] = gen_lowpart (V32QImode, operands[1]);
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})
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}
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,load,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "vec_extract_hi_v64qi"
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[(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m")
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[(set (match_operand:V32QI 0 "nonimmediate_operand" "=vm")
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(vec_select:V32QI
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(match_operand:V64QI 1 "register_operand" "v,v")
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(match_operand:V64QI 1 "register_operand" "v")
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(parallel [(const_int 32) (const_int 33)
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(const_int 34) (const_int 35)
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(const_int 36) (const_int 37)
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@ -8012,10 +8025,9 @@
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(const_int 62) (const_int 63)])))]
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"TARGET_AVX512F"
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"vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "memory" "none,store")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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@ -8038,9 +8050,9 @@
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"operands[1] = gen_lowpart (V16QImode, operands[1]);")
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(define_insn "vec_extract_hi_v32qi"
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[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m,v,m,v,m")
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[(set (match_operand:V16QI 0 "nonimmediate_operand" "=xm,vm,vm")
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(vec_select:V16QI
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(match_operand:V32QI 1 "register_operand" "x,x,v,v,v,v")
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(match_operand:V32QI 1 "register_operand" "x,v,v")
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(parallel [(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 20) (const_int 21)
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@ -8051,18 +8063,14 @@
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(const_int 30) (const_int 31)])))]
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"TARGET_AVX"
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"@
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vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
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vextract%~128\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %1, %0|%0, %1, 0x1}
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vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}
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vextracti32x4\t{$0x1, %g1, %0|%0, %g1, 0x1}"
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[(set_attr "type" "sselog")
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "isa" "*,*,avx512dq,avx512dq,avx512f,avx512f")
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(set_attr "memory" "none,store,none,store,none,store")
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(set_attr "prefix" "vex,vex,evex,evex,evex,evex")
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(set_attr "isa" "*,avx512dq,avx512f")
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(set_attr "prefix" "vex,evex,evex")
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(set_attr "mode" "OI")])
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;; Modes handled by vec_extract patterns.
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