config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*.
* config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*. * config/mips/mips.h (enum processor_type): Add PROCESSOR_OCTEON. (TARGET_OCTEON): New macro. (TARGET_CPU_CPP_BUILTINS): Define __OCTEON__ for Octeon. (MIPS_ISA_LEVEL_SPEC, MIPS_ARCH_FLOAT_SPEC): Handle -march=octeon. (ISA_HAS_POP): New macro. * config/mips/driver-native.c (host_detect_local_cpu): Handle Octeon. * config/mips/mips.c (mips_cpu_info_table, mips_rtx_cost_data): Handle Octeon. * config/mips/mips.md (cpu): Add octeon. (type): Add pop attribute value. (popcount<mode>2): New pattern. * doc/invoke.texi (-march=@var{arch}): Add octeon. testsuite/ * gcc.target/mips/octeon-pop-1.c: New test. From-SVN: r139554
This commit is contained in:
parent
807e74dbc6
commit
d97e6aca01
9 changed files with 88 additions and 5 deletions
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@ -1,3 +1,20 @@
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2008-08-24 Adam Nemet <anemet@caviumnetworks.com>
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* config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*.
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* config/mips/mips.h (enum processor_type): Add PROCESSOR_OCTEON.
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(TARGET_OCTEON): New macro.
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(TARGET_CPU_CPP_BUILTINS): Define __OCTEON__ for Octeon.
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(MIPS_ISA_LEVEL_SPEC, MIPS_ARCH_FLOAT_SPEC): Handle -march=octeon.
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(ISA_HAS_POP): New macro.
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* config/mips/driver-native.c (host_detect_local_cpu): Handle
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Octeon.
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* config/mips/mips.c (mips_cpu_info_table, mips_rtx_cost_data):
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Handle Octeon.
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* config/mips/mips.md (cpu): Add octeon.
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(type): Add pop attribute value.
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(popcount<mode>2): New pattern.
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* doc/invoke.texi (-march=@var{arch}): Add octeon.
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2008-08-24 Jan Hubicka <jh@suse.cz>
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* doc/invoke.texi (-fipa-cp-clone): New option.
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@ -1551,6 +1551,10 @@ mips64*-*-linux* | mipsisa64*-*-linux*)
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tm_file="${tm_file} mips/st.h"
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tmake_file="${tmake_file} mips/t-st"
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;;
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mips64octeon*-*-linux*)
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tm_defines="${tm_defines} MIPS_CPU_STRING_DEFAULT=\\\"octeon\\\""
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target_cpu_default=MASK_SOFT_FLOAT_ABI
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;;
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mipsisa64r2*-*-linux*)
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tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65"
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;;
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@ -67,6 +67,8 @@ host_detect_local_cpu (int argc, const char **argv)
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cpu = "sb1";
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else if (strstr (buf, "R5000") != NULL)
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cpu = "r5000";
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else if (strstr (buf, "Octeon") != NULL)
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cpu = "octeon";
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break;
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}
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@ -652,7 +652,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
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{ "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
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{ "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
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{ "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
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{ "xlr", PROCESSOR_XLR, 64, 0 }
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{ "xlr", PROCESSOR_XLR, 64, 0 },
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/* MIPS64 Release 2 processors. */
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{ "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
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};
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/* Default costs. If these are used for a processor we should look
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@ -851,6 +854,16 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
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},
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{ /* M4k */
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DEFAULT_COSTS
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},
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/* Octeon */
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{
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SOFT_FP_COSTS,
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COSTS_N_INSNS (5), /* int_mult_si */
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COSTS_N_INSNS (5), /* int_mult_di */
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COSTS_N_INSNS (72), /* int_div_si */
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COSTS_N_INSNS (72), /* int_div_di */
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* R3900 */
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COSTS_N_INSNS (2), /* fp_add */
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@ -50,6 +50,7 @@ enum processor_type {
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PROCESSOR_LOONGSON_2E,
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PROCESSOR_LOONGSON_2F,
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PROCESSOR_M4K,
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PROCESSOR_OCTEON,
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PROCESSOR_R3900,
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PROCESSOR_R6000,
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PROCESSOR_R4000,
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@ -253,6 +254,7 @@ enum mips_code_readable_setting {
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#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
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#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
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#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
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#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
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#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
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|| mips_arch == PROCESSOR_SB1A)
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#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
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@ -529,6 +531,10 @@ enum mips_code_readable_setting {
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if (TARGET_LOONGSON_VECTORS) \
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builtin_define ("__mips_loongson_vector_rev"); \
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\
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/* Historical Octeon macro. */ \
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if (TARGET_OCTEON) \
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builtin_define ("__OCTEON__"); \
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\
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/* Macros dependent on the C dialect. */ \
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if (preprocessing_asm_p ()) \
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{ \
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@ -693,7 +699,7 @@ enum mips_code_readable_setting {
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%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
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|march=34k*|march=74k*: -mips32r2} \
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%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
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%{march=mips64r2: -mips64r2} \
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%{march=mips64r2|march=octeon: -mips64r2} \
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%{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
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/* A spec that infers a -mhard-float or -msoft-float setting from an
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#define MIPS_ARCH_FLOAT_SPEC \
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"%{mhard-float|msoft-float|march=mips*:; \
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march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
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|march=34kc|march=74kc|march=5kc: -msoft-float; \
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|march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
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march=*: -mhard-float}"
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/* A spec condition that matches 32-bit options. It only works if
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(target_flags_explicit & MASK_LLSC \
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? TARGET_LLSC && !TARGET_MIPS16 \
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: ISA_HAS_LL_SC)
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/* ISA includes the pop instruction. */
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#define ISA_HAS_POP TARGET_OCTEON
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/* Add -G xx support. */
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@ -344,6 +344,7 @@
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;; slt set less than instructions
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;; signext sign extend instructions
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;; clz the clz and clo instructions
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;; pop the pop instruction
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;; trap trap if instructions
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;; imul integer multiply 2 operands
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;; imul3 integer multiply 3 operands
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(define_attr "type"
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"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
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prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
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shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
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shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
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fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
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frsqrt2,multi,nop,ghost"
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(cond [(eq_attr "jal" "!unset") (const_string "call")
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;; Attribute describing the processor. This attribute must match exactly
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;; with the processor_type enumeration in mips.h.
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(define_attr "cpu"
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"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
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"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
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(const (symbol_ref "mips_tune")))
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;; The type of hardware hazard associated with this instruction.
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"<d>clz\t%0,%1"
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[(set_attr "type" "clz")
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(set_attr "mode" "<MODE>")])
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;;
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;; ...................
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;;
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;; Count number of set bits.
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;;
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;; ...................
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;;
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(define_insn "popcount<mode>2"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
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"ISA_HAS_POP"
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"<d>pop\t%0,%1"
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[(set_attr "type" "pop")
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(set_attr "mode" "<MODE>")])
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;;
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;; ....................
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@ -11999,6 +11999,7 @@ The processor names are:
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@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
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@samp{loongson2e}, @samp{loongson2f},
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@samp{m4k},
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@samp{octeon},
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@samp{orion},
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@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
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@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},
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@ -1,3 +1,7 @@
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2008-08-24 Adam Nemet <anemet@caviumnetworks.com>
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* gcc.target/mips/octeon-pop-1.c: New test.
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2008-08-24 Tobias Burnus <burnus@net-b.de>
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PR fortran/37201
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16
gcc/testsuite/gcc.target/mips/octeon-pop-1.c
Normal file
16
gcc/testsuite/gcc.target/mips/octeon-pop-1.c
Normal file
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/* { dg-do compile } */
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/* { dg-mips-options "-O -march=octeon -mgp64" } */
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/* { dg-final { scan-assembler "\tpop\t" } } */
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/* { dg-final { scan-assembler "\tdpop\t" } } */
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NOMIPS16 int
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f (long long a)
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{
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return __builtin_popcountll (a);
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}
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NOMIPS16 int
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g (int a)
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{
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return __builtin_popcount (a);
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}
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