IA MCU psABI support: GCC changes
This patch introduces basic IA MCU psABI support into GCC. * configure.ac (ospace_frag): Enable for i?86*-*-elfiamcu target. * configure: Regenerate. gcc/ * config.gcc: Support i[34567]86-*-elfiamcu target. * config/i386/iamcu.h: New. * config/i386/i386.opt: Add -miamcu. * doc/invoke.texi: Document -miamcu. * common/config/i386/i386-common.c (ix86_handle_option): Turn off x87/MMX/SSE/AVX codegen for -miamcu. * config/i386/i386-c.c (ix86_target_macros_internal): Define __iamcu/__iamcu__ for -miamcu. * config/i386/i386.h (PREFERRED_STACK_BOUNDARY_DEFAULT): Set to MIN_STACK_BOUNDARY if TARGET_IAMCU is true. (BIGGEST_ALIGNMENT): Set to 32 if TARGET_IAMCU is true. * config/i386/i386.c (ix86_option_override_internal): Ignore and warn -mregparm for Intel MCU. Turn on -mregparm=3 for Intel MCU by default. Default long double to 64-bit for Intel MCU. Turn on -freg-struct-return for Intel MCU. Issue an error when -miamcu is used in 64-bit or x32 mode or if x87, MMX, SSE or AVX is turned on. (function_arg_advance_32): Pass value whose size is no larger than 8 bytes in registers for Intel MCU. (function_arg_32): Likewise. (ix86_return_in_memory): Return value whose size is no larger than 8 bytes in registers for Intel MCU. (iamcu_alignment): New function. (ix86_data_alignment): Call iamcu_alignment if TARGET_IAMCU is true. (ix86_local_alignment): Don't increase alignment for Intel MCU. (x86_field_alignment): Return iamcu_alignment if TARGET_IAMCU is true. From-SVN: r225197
This commit is contained in:
H.J. Lu
H.J. Lu
parent
3db55b2b6d
commit
d90639476f
12 changed files with 216 additions and 12 deletions
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@ -1,3 +1,9 @@
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2015-06-30 H.J. Lu <hongjiu.lu@intel.com>
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* configure.ac (ospace_frag): Enable for i?86*-*-elfiamcu
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target.
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* configure: Regenerate.
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2015-06-23 Ludovic Courtès <ludo@gnu.org>
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* MAINTAINERS (Write After Approval): Add myself.
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2
configure
vendored
2
configure
vendored
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@ -6914,7 +6914,7 @@ case "${enable_target_optspace}:${target}" in
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:d30v-*)
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ospace_frag="config/mt-d30v"
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;;
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:m32r-* | :d10v-* | :fr30-*)
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:m32r-* | :d10v-* | :fr30-* | :i?86*-*-elfiamcu)
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ospace_frag="config/mt-ospace"
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;;
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no:* | :*)
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@ -2560,7 +2560,7 @@ case "${enable_target_optspace}:${target}" in
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:d30v-*)
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ospace_frag="config/mt-d30v"
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;;
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:m32r-* | :d10v-* | :fr30-*)
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:m32r-* | :d10v-* | :fr30-* | :i?86*-*-elfiamcu)
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ospace_frag="config/mt-ospace"
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;;
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no:* | :*)
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@ -1,3 +1,34 @@
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2015-06-30 H.J. Lu <hongjiu.lu@intel.com>
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* config.gcc: Support i[34567]86-*-elfiamcu target.
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* config/i386/iamcu.h: New.
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* config/i386/i386.opt: Add -miamcu.
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* doc/invoke.texi: Document -miamcu.
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* common/config/i386/i386-common.c (ix86_handle_option): Turn
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off x87/MMX/SSE/AVX codegen for -miamcu.
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* config/i386/i386-c.c (ix86_target_macros_internal): Define
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__iamcu/__iamcu__ for -miamcu.
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* config/i386/i386.h (PREFERRED_STACK_BOUNDARY_DEFAULT): Set
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to MIN_STACK_BOUNDARY if TARGET_IAMCU is true.
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(BIGGEST_ALIGNMENT): Set to 32 if TARGET_IAMCU is true.
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* config/i386/i386.c (ix86_option_override_internal): Ignore and
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warn -mregparm for Intel MCU. Turn on -mregparm=3 for Intel
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MCU by default. Default long double to 64-bit for Intel MCU.
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Turn on -freg-struct-return for Intel MCU. Issue an error when
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-miamcu is used in 64-bit or x32 mode or if x87, MMX, SSE or
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AVX is turned on.
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(function_arg_advance_32): Pass value whose size is no larger
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than 8 bytes in registers for Intel MCU.
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(function_arg_32): Likewise.
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(ix86_return_in_memory): Return value whose size is no larger
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than 8 bytes in registers for Intel MCU.
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(iamcu_alignment): New function.
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(ix86_data_alignment): Call iamcu_alignment if TARGET_IAMCU is
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true.
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(ix86_local_alignment): Don't increase alignment for Intel MCU.
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(x86_field_alignment): Return iamcu_alignment if TARGET_IAMCU is
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true.
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2015-06-30 Marek Polacek <polacek@redhat.com>
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* match.pd (X - (X / Y) * Y): Use convert1 and convert2. Convert
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@ -223,7 +223,7 @@ along with GCC; see the file COPYING3. If not see
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bool
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ix86_handle_option (struct gcc_options *opts,
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struct gcc_options *opts_set ATTRIBUTE_UNUSED,
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struct gcc_options *opts_set,
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const struct cl_decoded_option *decoded,
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location_t loc)
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{
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@ -232,6 +232,20 @@ ix86_handle_option (struct gcc_options *opts,
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switch (code)
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{
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case OPT_miamcu:
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if (value)
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{
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/* Turn off x87/MMX/SSE/AVX codegen for -miamcu. */
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opts->x_target_flags &= ~MASK_80387;
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opts_set->x_target_flags |= MASK_80387;
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opts->x_ix86_isa_flags &= ~(OPTION_MASK_ISA_MMX_UNSET
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| OPTION_MASK_ISA_SSE_UNSET);
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opts->x_ix86_isa_flags_explicit |= (OPTION_MASK_ISA_MMX_UNSET
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| OPTION_MASK_ISA_SSE_UNSET);
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}
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return true;
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case OPT_mmmx:
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if (value)
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{
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@ -1389,6 +1389,9 @@ x86_64-*-darwin*)
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tmake_file="${tmake_file} ${cpu_type}/t-darwin64 t-slibgcc"
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tm_file="${tm_file} ${cpu_type}/darwin64.h"
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;;
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i[34567]86-*-elfiamcu)
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tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h newlib-stdint.h i386/iamcu.h"
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;;
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i[34567]86-*-elf*)
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tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h newlib-stdint.h i386/i386elf.h"
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;;
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@ -425,6 +425,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__CLWB__");
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if (isa_flag & OPTION_MASK_ISA_MWAITX)
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def_or_undef (parse_in, "__MWAITX__");
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if (TARGET_IAMCU)
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{
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def_or_undef (parse_in, "__iamcu");
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def_or_undef (parse_in, "__iamcu__");
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}
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}
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@ -3433,6 +3433,10 @@ ix86_option_override_internal (bool main_args_p,
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|| TARGET_16BIT_P (opts->x_ix86_isa_flags))
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ABI_X32;
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#endif
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if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
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&& TARGET_IAMCU_P (opts->x_target_flags))
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sorry ("Intel MCU psABI isn%'t supported in %s mode",
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TARGET_X32_P (opts->x_ix86_isa_flags) ? "x32" : "64-bit");
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}
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#endif
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@ -3817,6 +3821,20 @@ ix86_option_override_internal (bool main_args_p,
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if (TARGET_X32 && (ix86_isa_flags & OPTION_MASK_ISA_MPX))
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error ("Intel MPX does not support x32");
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if (TARGET_IAMCU_P (opts->x_target_flags))
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{
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/* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
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if (TARGET_80387_P (opts->x_target_flags))
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sorry ("X87 FPU isn%'t supported in Intel MCU psABI");
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else if ((opts->x_ix86_isa_flags & (OPTION_MASK_ISA_MMX
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| OPTION_MASK_ISA_SSE
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| OPTION_MASK_ISA_AVX)))
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sorry ("%s isn%'t supported in Intel MCU psABI",
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TARGET_MMX_P (opts->x_ix86_isa_flags)
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? "MMX"
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: TARGET_SSE_P (opts->x_ix86_isa_flags) ? "SSE" : "AVX");
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}
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if (!strcmp (opts->x_ix86_arch_string, "generic"))
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error ("generic CPU can be used only for %stune=%s %s",
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prefix, suffix, sw);
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@ -3904,7 +3922,16 @@ ix86_option_override_internal (bool main_args_p,
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if (opts->x_flag_asynchronous_unwind_tables == 2)
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opts->x_flag_asynchronous_unwind_tables = !USE_IX86_FRAME_POINTER;
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if (opts->x_flag_pcc_struct_return == 2)
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opts->x_flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
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{
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/* Intel MCU psABI specifies that -freg-struct-return should
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be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
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we check -miamcu so that -freg-struct-return is always
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turned on if -miamcu is used. */
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if (TARGET_IAMCU_P (opts->x_target_flags))
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opts->x_flag_pcc_struct_return = 0;
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else
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opts->x_flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
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}
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}
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ix86_tune_cost = processor_target_table[ix86_tune].cost;
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@ -3923,6 +3950,8 @@ ix86_option_override_internal (bool main_args_p,
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{
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if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
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warning (0, "-mregparm is ignored in 64-bit mode");
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else if (TARGET_IAMCU_P (opts->x_target_flags))
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warning (0, "-mregparm is ignored for Intel MCU psABI");
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if (opts->x_ix86_regparm > REGPARM_MAX)
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{
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error ("-mregparm=%d is not between 0 and %d",
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@ -3930,7 +3959,8 @@ ix86_option_override_internal (bool main_args_p,
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opts->x_ix86_regparm = 0;
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}
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}
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if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
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if (TARGET_IAMCU_P (opts->x_target_flags)
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|| TARGET_64BIT_P (opts->x_ix86_isa_flags))
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opts->x_ix86_regparm = REGPARM_MAX;
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/* Default align_* from the processor table. */
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@ -4334,8 +4364,9 @@ ix86_option_override_internal (bool main_args_p,
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opts->x_recip_mask &= ~(RECIP_MASK_ALL & ~opts->x_recip_mask_explicit);
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/* Default long double to 64-bit for 32-bit Bionic and to __float128
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for 64-bit Bionic. */
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if (TARGET_HAS_BIONIC
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for 64-bit Bionic. Also default long double to 64-bit for Intel
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MCU psABI. */
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if ((TARGET_HAS_BIONIC || TARGET_IAMCU)
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&& !(opts_set->x_target_flags
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& (MASK_LONG_DOUBLE_64 | MASK_LONG_DOUBLE_128)))
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opts->x_target_flags |= (TARGET_64BIT
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@ -7455,6 +7486,15 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
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int res = 0;
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bool error_p = NULL;
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if (TARGET_IAMCU)
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{
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/* Intel MCU psABI passes scalars and aggregates no larger than 8
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bytes in registers. */
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if (bytes <= 8)
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goto pass_in_reg;
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return res;
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}
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switch (mode)
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{
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default:
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@ -7469,6 +7509,7 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
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case SImode:
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case HImode:
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case QImode:
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pass_in_reg:
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cum->words += words;
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cum->nregs -= words;
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cum->regno += words;
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@ -7702,6 +7743,15 @@ function_arg_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
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if (mode == VOIDmode)
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return constm1_rtx;
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if (TARGET_IAMCU)
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{
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/* Intel MCU psABI passes scalars and aggregates no larger than 8
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bytes in registers. */
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if (bytes <= 8)
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goto pass_in_reg;
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return NULL_RTX;
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}
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switch (mode)
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{
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default:
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@ -7715,6 +7765,7 @@ function_arg_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
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case SImode:
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case HImode:
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case QImode:
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pass_in_reg:
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if (words <= cum->nregs)
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{
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int regno = cum->regno;
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@ -8561,11 +8612,16 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
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}
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else
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{
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size = int_size_in_bytes (type);
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/* Intel MCU psABI returns scalars and aggregates no larger than 8
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bytes in registers. */
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if (TARGET_IAMCU)
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return size > 8;
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if (mode == BLKmode)
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return true;
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size = int_size_in_bytes (type);
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if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
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return false;
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@ -27334,6 +27390,34 @@ ix86_constant_alignment (tree exp, int align)
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return align;
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}
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/* Compute the alignment for a variable for Intel MCU psABI. TYPE is
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the data type, and ALIGN is the alignment that the object would
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ordinarily have. */
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static int
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iamcu_alignment (tree type, int align)
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{
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enum machine_mode mode;
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if (align < 32 || TYPE_USER_ALIGN (type))
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return align;
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/* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
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bytes. */
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mode = TYPE_MODE (strip_array_types (type));
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switch (GET_MODE_CLASS (mode))
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{
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case MODE_INT:
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case MODE_COMPLEX_INT:
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case MODE_COMPLEX_FLOAT:
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case MODE_FLOAT:
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case MODE_DECIMAL_FLOAT:
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return 32;
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default:
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return align;
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}
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}
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/* Compute the alignment for a static variable.
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TYPE is the data type, and ALIGN is the alignment that
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the object would ordinarily have. The value of this function is used
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@ -27368,6 +27452,9 @@ ix86_data_alignment (tree type, int align, bool opt)
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case ix86_align_data_type_cacheline: break;
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}
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if (TARGET_IAMCU)
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align = iamcu_alignment (type, align);
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if (opt
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&& AGGREGATE_TYPE_P (type)
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&& TYPE_SIZE (type)
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@ -27477,6 +27564,10 @@ ix86_local_alignment (tree exp, machine_mode mode,
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return align;
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}
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/* Don't increase alignment for Intel MCU psABI. */
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if (TARGET_IAMCU)
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return align;
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/* x86-64 ABI requires arrays greater than 16 bytes to be aligned
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to 16byte boundary. Exact wording is:
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@ -43187,6 +43278,8 @@ x86_field_alignment (tree field, int computed)
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if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
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return computed;
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if (TARGET_IAMCU)
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return iamcu_alignment (type, computed);
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mode = TYPE_MODE (strip_array_types (type));
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if (mode == DFmode || mode == DCmode
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|| GET_MODE_CLASS (mode) == MODE_INT
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@ -756,7 +756,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
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both 32bit and 64bit, to support codes that need 128 bit stack
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alignment for SSE instructions, but can't realign the stack. */
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#define PREFERRED_STACK_BOUNDARY_DEFAULT 128
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#define PREFERRED_STACK_BOUNDARY_DEFAULT \
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(TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
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/* 1 if -mstackrealign should be turned on by default. It will
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generate an alternate prologue and epilogue that realigns the
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@ -803,7 +804,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
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#define BIGGEST_ALIGNMENT \
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(TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))
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(TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : (TARGET_IAMCU ? 32 : 128)))
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/* Maximum stack alignment. */
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#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
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|
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@ -514,6 +514,10 @@ Clear all tune features
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mdump-tune-features
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Target RejectNegative Var(ix86_dump_tunes) Init(0)
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miamcu
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Target Report Mask(IAMCU)
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Generate code that conforms to Intel MCU psABI
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mabi=
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Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
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Generate code that conforms to the given ABI
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|
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42
gcc/config/i386/iamcu.h
Normal file
42
gcc/config/i386/iamcu.h
Normal file
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@ -0,0 +1,42 @@
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/* Definitions of target machine for Intel MCU psABI.
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Copyright (C) 2015 Free Software Foundation, Inc.
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|
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This file is part of GCC.
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|
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GCC is free software; you can redistribute it and/or modify
|
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Intel MCU has no 80387. Default to Intel MCU psABI. */
|
||||
#undef TARGET_SUBTARGET_DEFAULT
|
||||
#define TARGET_SUBTARGET_DEFAULT MASK_IAMCU
|
||||
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "--32 -march=iamcu"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC "-m elf_iamcu"
|
||||
|
||||
#undef ENDFILE_SPEC
|
||||
#define ENDFILE_SPEC ""
|
||||
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC "crt0.o%s"
|
||||
|
||||
#undef LIB_SPEC
|
||||
#define LIB_SPEC "--start-group -lc -lgloss --end-group"
|
||||
|
|
@ -1096,7 +1096,7 @@ See RS/6000 and PowerPC Options.
|
|||
-mpc32 -mpc64 -mpc80 -mstackrealign @gol
|
||||
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
|
||||
-mcmodel=@var{code-model} -mabi=@var{name} -maddress-mode=@var{mode} @gol
|
||||
-m32 -m64 -mx32 -m16 -mlarge-data-threshold=@var{num} @gol
|
||||
-m32 -m64 -mx32 -m16 -miamcu -mlarge-data-threshold=@var{num} @gol
|
||||
-msse2avx -mfentry -mrecord-mcount -mnop-mcount -m8bit-idiv @gol
|
||||
-mavx256-split-unaligned-load -mavx256-split-unaligned-store @gol
|
||||
-malign-data=@var{type} -mstack-protector-guard=@var{guard}}
|
||||
|
|
@ -23289,10 +23289,12 @@ on x86-64 processors in 64-bit environments.
|
|||
@itemx -m64
|
||||
@itemx -mx32
|
||||
@itemx -m16
|
||||
@itemx -miamcu
|
||||
@opindex m32
|
||||
@opindex m64
|
||||
@opindex mx32
|
||||
@opindex m16
|
||||
@opindex miamcu
|
||||
Generate code for a 16-bit, 32-bit or 64-bit environment.
|
||||
The @option{-m32} option sets @code{int}, @code{long}, and pointer types
|
||||
to 32 bits, and
|
||||
|
|
@ -23311,6 +23313,9 @@ The @option{-m16} option is the same as @option{-m32}, except for that
|
|||
it outputs the @code{.code16gcc} assembly directive at the beginning of
|
||||
the assembly output so that the binary can run in 16-bit mode.
|
||||
|
||||
The @option{-miamcu} option generates code which conforms to Intel MCU
|
||||
psABI. It requires the @option{-m32} option to be turned on.
|
||||
|
||||
@item -mno-red-zone
|
||||
@opindex mno-red-zone
|
||||
Do not use a so-called ``red zone'' for x86-64 code. The red zone is mandated
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue