procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

MSP430: Tweaks to generation of 430X instructions

Browse source 
gcc/ChangeLog:

2019-10-24  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* config/msp430/constraints.md: Allow post_inc for "Ya" constraint.
	* config/msp430/msp430.md (430x_shift_left): Use RLAM when the constant
	shift amount is between 1 and 4.
	(430x_arithmetic_shift_right): Use RRAM when the constant shift amount
	is between 1 and 4.

gcc/testsuite/ChangeLog:

2019-10-24  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* gcc.target/msp430/emulate-slli.c: Skip for -mcpu=msp430.
	Add shift by a constant 5 bits.
	Update scan-assembler directives.
	* gcc.target/msp430/emulate-srai.c: Likewise.
	* gcc.target/msp430/emulate-srli.c: Skip for -mcpu=msp430.

From-SVN: r277394
This commit is contained in:
Jozef Lawrynowicz 2019-10-24 13:34:54 +00:00 • committed by Jozef Lawrynowicz
parent e227594789
commit d8e4dc54a6
7 changed files with 36 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
gcc/ChangeLog
View file

@ -1,3 +1,11 @@
2019-10-24 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/constraints.md: Allow post_inc for "Ya" constraint.
* config/msp430/msp430.md (430x_shift_left): Use RLAM when the constant
shift amount is between 1 and 4.
(430x_arithmetic_shift_right): Use RRAM when the constant shift amount
is between 1 and 4.
2019-10-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/92205

1
gcc/config/msp430/constraints.md
View file

@ -82,6 +82,7 @@
(match_test ("CONST_INT_P (XEXP (XEXP (op, 0), 1))"))
(match_test ("IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), HOST_WIDE_INT_M1U << 15, (1 << 15)-1)"))))
(match_code "reg" "0")
(match_code "post_inc" "0")
)))
(define_constraint "Yc"

12
gcc/config/msp430/msp430.md
View file

@ -875,8 +875,10 @@
(match_operand 2 "immediate_operand" "n")))]
"msp430x"
"*
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 16)
return \"rpt\t%2 { rlax.w\t%0\";
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 5)
return \"RLAM.W\t%2, %0\";
else if (INTVAL (operands[2]) >= 5 && INTVAL (operands[2]) < 16)
return \"RPT\t%2 { RLAX.W\t%0\";
return \"# nop left shift\";
"
)
@ -960,8 +962,10 @@
(match_operand 2 "immediate_operand" "n")))]
"msp430x"
"*
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 16)
return \"rpt\t%2 { rrax.w\t%0\";
if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 5)
return \"RRAM.W\t%2, %0\";
else if (INTVAL (operands[2]) >= 5 && INTVAL (operands[2]) < 16)
return \"RPT\t%2 { RRAX.W\t%0\";
return \"# nop arith right shift\";
"
)

8
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,11 @@
2019-10-24 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* gcc.target/msp430/emulate-slli.c: Skip for -mcpu=msp430.
Add shift by a constant 5 bits.
Update scan-assembler directives.
* gcc.target/msp430/emulate-srai.c: Likewise.
* gcc.target/msp430/emulate-srli.c: Skip for -mcpu=msp430.
2019-10-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/92205

6
gcc/testsuite/gcc.target/msp430/emulate-slli.c
View file

@ -1,15 +1,19 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" } { "" } } */
/* { dg-options "-Os" } */
/* { dg-final { scan-assembler-not "mspabi_slli" } } */
/* { dg-final { scan-assembler "rlax" } } */
/* { dg-final { scan-assembler "RLAM.W\t#4" } } */
/* { dg-final { scan-assembler "RPT\t#5 \{ RLAX.W" } } */
/* Ensure that HImode shifts with source operand in memory are emulated with a
rotate instructions. */
int a;
int b;
void
foo (void)
{
a = a << 4;
b = b << 5;
}

6
gcc/testsuite/gcc.target/msp430/emulate-srai.c
View file

@ -1,15 +1,19 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" } { "" } } */
/* { dg-options "-Os" } */
/* { dg-final { scan-assembler-not "mspabi_srai" } } */
/* { dg-final { scan-assembler "rrax" } } */
/* { dg-final { scan-assembler "RRAM.W\t#4" } } */
/* { dg-final { scan-assembler "RPT\t#5 \{ RRAX.W" } } */
/* Ensure that HImode shifts with source operand in memory are emulated with a
rotate instructions. */
int a;
int b;
void
foo (void)
{
a = a >> 4;
b = b >> 5;
}

1
gcc/testsuite/gcc.target/msp430/emulate-srli.c
View file

@ -1,4 +1,5 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" } { "" } } */
/* { dg-options "-Os" } */
/* { dg-final { scan-assembler-not "mspabi_srli" } } */
/* { dg-final { scan-assembler "rrum" } } */