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[PR83370][AARCH64]Use tighter register constraint for sibcall patterns.

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In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
temporary register.

When the compiler is performing sibcall optimization. It has the chance to use
ip0/ip1 register for indirect function call to hold the address. However,
those two register might be clobbered by the epilogue code which makes the
last sibcall instruction invalid.

The patch here renames the register class CALLER_SAVE_REGS to TAILCALL_ADDR_REGS
to reflect its usage, and remove IP registers from this class.

gcc/

2018-02-01  Renlin Li  <renlin.li@arm.com>

	PR target/83370
	* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
	TAILCALL_ADDR_REGS.
	(aarch64_register_move_cost): Likewise.
	* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS. Remove IP registers.
	* config/aarch64/aarch64.md (Ucs): Update register constraint.

gcc/testsuite/

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

	PR target/83370
	* gcc.target/aarch64/pr83370.c: New.

From-SVN: r257294
This commit is contained in:
Renlin Li 2018-02-01 13:02:24 +00:00
parent dc3b4a20b5
commit d677263e6c
6 changed files with 48 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
gcc/ChangeLog
View file

@ -1,3 +1,16 @@
2018-02-01 Renlin Li <renlin.li@arm.com>
PR target/83370
* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
TAILCALL_ADDR_REGS.
(aarch64_register_move_cost): Likewise.
* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
TAILCALL_ADDR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
TAILCALL_ADDR_REGS. Remove IP registers.
* config/aarch64/aarch64.md (Ucs): Update register constraint.
2018-02-01 Richard Biener <rguenther@suse.de>
* domwalk.h (dom_walker::dom_walker): Add additional constructor

6
gcc/config/aarch64/aarch64.c
View file

@ -7523,7 +7523,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode)
unsigned int nregs;
switch (regclass)
{
case CALLER_SAVE_REGS:
case TAILCALL_ADDR_REGS:
case POINTER_REGS:
case GENERAL_REGS:
case ALL_REGS:
@ -9687,10 +9687,10 @@ aarch64_register_move_cost (machine_mode mode,
= aarch64_tune_params.regmove_cost;
/* Caller save and pointer regs are equivalent to GENERAL_REGS. */
if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS)
to = GENERAL_REGS;
if (from == CALLER_SAVE_REGS || from == POINTER_REGS)
if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS)
from = GENERAL_REGS;
/* Moving between GPR and stack cost is the same as GP2GP. */

6
gcc/config/aarch64/aarch64.h
View file

@ -507,7 +507,7 @@ extern unsigned aarch64_architecture_version;
enum reg_class
{
NO_REGS,
CALLER_SAVE_REGS,
TAILCALL_ADDR_REGS,
GENERAL_REGS,
STACK_REG,
POINTER_REGS,
@ -526,7 +526,7 @@ enum reg_class
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"CALLER_SAVE_REGS", \
"TAILCALL_ADDR_REGS", \
"GENERAL_REGS", \
"STACK_REG", \
"POINTER_REGS", \
@ -542,7 +542,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
{ 0x0004ffff, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\
{ 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
{ 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
{ 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \

4
gcc/config/aarch64/constraints.md
View file

@ -21,8 +21,8 @@
(define_register_constraint "k" "STACK_REG"
"@internal The stack register.")
(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
"@internal The caller save registers.")
(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
"@internal Registers suitable for an indirect tail call")
(define_register_constraint "w" "FP_REGS"
"Floating point and SIMD vector registers.")

5
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2018-02-01 Richard Sandiford <richard.sandiford@linaro.org>
PR target/83370
* gcc.target/aarch64/pr83370.c: New.
2018-02-01 Richard Biener <rguenther@suse.de>
* gcc.dg/graphite/pr35356-1.c: Adjust.

22
gcc/testsuite/gcc.target/aarch64/pr83370.c Normal file
View file

@ -0,0 +1,22 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
typedef void (*fun) (void);
void __attribute__ ((noipa))
f (fun x1)
{
register fun x2 asm ("x16");
int arr[5000];
int *volatile ptr = arr;
asm ("mov %0, %1" : "=r" (x2) : "r" (x1));
x2 ();
}
void g (void) {}
int
main (void)
{
f (g);
}