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RISC-V: Remove XFAIL of ssa-dom-cse-2.c

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Confirm RISC-V is able to CSE this case no matter whether we enable RVV or not.

Remove XFAIL,  to fix:
XPASS: gcc.dg/tree-ssa/ssa-dom-cse-2.c scan-tree-dump optimized "return 28;"

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Remove riscv.
This commit is contained in:
Juzhe-Zhong 2023-10-11 11:25:07 +08:00 • committed by Lehua Ding
parent e75bf1985f
commit d4de593d36
1 changed files with 1 additions and 1 deletions
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gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
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@ -27,4 +27,4 @@ foo ()
but the loop reads only one element at a time, and DOM cannot resolve these.
The same happens on powerpc depending on the SIMD support available. */
/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* mmix-knuth-mmixware } || { { { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } || aarch64_sve } || { arm*-*-* && { ! arm_neon } } } } } } } */
/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* mmix-knuth-mmixware } || { { { lp64 && { powerpc*-*-* sparc*-*-* } } || aarch64_sve } || { arm*-*-* && { ! arm_neon } } } } } } } */