PR rtl-optimization/96692: ((A|B)^C)^A using andn with -mbmi on x86.
This patch addresses PR rtl-optimization/96692 on x86_64, by providing a set of combine splitters to convert the three operation ((A|B)^C)^D into a two operation sequence using andn when either A or B is the same register as C or D. This is essentially a reassociation problem that's only a win if the target supports an and-not instruction (as with -mbmi). Hence for the new test case: int f(int a, int b, int c) { return (a ^ b) ^ (a | c); } GCC on x86_64-pc-linux-gnu wth -O2 -mbmi would previously generate: xorl %edi, %esi orl %edx, %edi movl %esi, %eax xorl %edi, %eax ret but with this patch now generates: andn %edx, %edi, %eax xorl %esi, %eax ret 2022-07-05 Roger Sayle <roger@nextmovesoftware.com> Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog PR rtl-optimization/96692 * config/i386/i386.md (define_split): Split ((A | B) ^ C) ^ D as (X & ~Y) ^ Z on target BMI when either C or D is A or B. gcc/testsuite/ChangeLog PR rtl-optimization/96692 * gcc.target/i386/bmi-andn-4.c: New test case.
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@ -10522,6 +10522,82 @@
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(set (match_dup 0) (match_op_dup 1
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[(and:SI (match_dup 3) (match_dup 2))
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(const_int 0)]))])
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;; Variant 1 of 4: Split ((A | B) ^ A) ^ C as (B & ~A) ^ C.
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(define_split
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[(set (match_operand:SWI48 0 "register_operand")
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(xor:SWI48
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(xor:SWI48
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(ior:SWI48 (match_operand:SWI48 1 "register_operand")
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(match_operand:SWI48 2 "nonimmediate_operand"))
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(match_dup 1))
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(match_operand:SWI48 3 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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[(parallel
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[(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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;; Variant 2 of 4: Split ((A | B) ^ B) ^ C as (A & ~B) ^ C.
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(define_split
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[(set (match_operand:SWI48 0 "register_operand")
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(xor:SWI48
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(xor:SWI48
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(ior:SWI48 (match_operand:SWI48 1 "register_operand")
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(match_operand:SWI48 2 "register_operand"))
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(match_dup 2))
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(match_operand:SWI48 3 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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[(parallel
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[(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 2)) (match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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;; Variant 3 of 4: Split ((A | B) ^ C) ^ A as (B & ~A) ^ C.
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(define_split
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[(set (match_operand:SWI48 0 "register_operand")
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(xor:SWI48
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(xor:SWI48
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(ior:SWI48 (match_operand:SWI48 1 "register_operand")
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(match_operand:SWI48 2 "nonimmediate_operand"))
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(match_operand:SWI48 3 "nonimmediate_operand"))
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(match_dup 1)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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[(parallel
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[(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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;; Variant 4 of 4: Split ((A | B) ^ C) ^ B as (A & ~B) ^ C.
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(define_split
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[(set (match_operand:SWI48 0 "register_operand")
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(xor:SWI48
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(xor:SWI48
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(ior:SWI48 (match_operand:SWI48 1 "register_operand")
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(match_operand:SWI48 2 "register_operand"))
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(match_operand:SWI48 3 "nonimmediate_operand"))
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(match_dup 2)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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[(parallel
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[(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 2)) (match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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;; Logical inclusive and exclusive OR instructions
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9
gcc/testsuite/gcc.target/i386/bmi-andn-4.c
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9
gcc/testsuite/gcc.target/i386/bmi-andn-4.c
Normal file
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@ -0,0 +1,9 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mbmi" } */
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int f(int a, int b, int c)
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{
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return (a ^ b) ^ (a | c);
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}
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/* { dg-final { scan-assembler "andn\[ \\t\]+" } } */
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