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RISC-V: Allow register pairs for 64-bit target.

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gcc/
	* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.

From-SVN: r257114
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Jim Wilson 2018-01-27 00:00:11 +00:00 • committed by Jim Wilson
parent cc24ff0dc2
commit d3f952c5e0
2 changed files with 6 additions and 0 deletions
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gcc/ChangeLog
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@ -1,5 +1,7 @@
2018-01-26 Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.
* config/riscv/elf.h (LIB_SPEC): Don't include -lgloss when nosys.specs
specified.

4
gcc/config/riscv/riscv.h
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@ -158,6 +158,10 @@ along with GCC; see the file COPYING3. If not see
#define PCC_BITFIELD_TYPE_MATTERS 1
/* An integer expression for the size in bits of the largest integer machine
mode that should actually be used. We allow pairs of registers. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
/* If defined, a C expression to compute the alignment for a static
variable. TYPE is the data type, and ALIGN is the alignment that
the object would ordinarily have. The value of this macro is used