re PR target/11259 ([avr] gcc Double 'andi' missed optimization)
PR target/11259 * config/avr/avr.md (UNSPEC_SWAP): New constants. (*swap): New insn pattern. (*ashlqi3): Rename from ashlqi3 insn pattern. (ashlqi3): New expanders. (*lshrqi3): Rename from lshrqi3 insn pattern. (lshrqi3): New expanders. (ashlqi3_const4, ashlqi3_const5, ashlqi3_const6, lshrqi3_const4, lshrqi3_const5, lshrqi3_const6): New splitters. (andi, ashlqi3_l_const4, ashlqi3_l_const5, ashlqi3_l_const6, lshrqi3_l_const4, lshrqi3_l_const5, lshrqi3_l_const6): Define peephole2 patterns. From-SVN: r139502
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Anatoly Sokolov
Anatoly Sokolov
parent
36159cf857
commit
d3dd4dbd1d
2 changed files with 184 additions and 2 deletions
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@ -1,3 +1,18 @@
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2008-08-22 Anatoly Sokolov <aesok@post.ru>
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PR target/11259
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* config/avr/avr.md (UNSPEC_SWAP): New constants.
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(*swap): New insn pattern.
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(*ashlqi3): Rename from ashlqi3 insn pattern.
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(ashlqi3): New expanders.
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(*lshrqi3): Rename from lshrqi3 insn pattern.
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(lshrqi3): New expanders.
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(ashlqi3_const4, ashlqi3_const5, ashlqi3_const6, lshrqi3_const4,
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lshrqi3_const5, lshrqi3_const6): New splitters.
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(andi, ashlqi3_l_const4, ashlqi3_l_const5, ashlqi3_l_const6,
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lshrqi3_l_const4, lshrqi3_l_const5, lshrqi3_l_const6): Define
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peephole2 patterns.
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2008-08-22 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/37078
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@ -54,6 +54,7 @@
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(UNSPEC_INDEX_JMP 1)
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(UNSPEC_SEI 2)
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(UNSPEC_CLI 3)
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(UNSPEC_SWAP 4)
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(UNSPECV_PROLOGUE_SAVES 0)
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(UNSPECV_EPILOGUE_RESTORES 1)
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@ -1261,6 +1262,19 @@
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[(set_attr "length" "4,4")
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(set_attr "cc" "set_n,set_n")])
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(define_peephole2 ; andi
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[(set (match_operand:QI 0 "d_register_operand" "")
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(and:QI (match_dup 0)
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(match_operand:QI 1 "const_int_operand" "")))
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(set (match_dup 0)
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(and:QI (match_dup 0)
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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{
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operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
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})
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;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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;; ior
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@ -1389,10 +1403,57 @@
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[(set_attr "length" "4")
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(set_attr "cc" "set_n")])
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;; swap
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(define_insn "*swap"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(unspec:QI [(match_operand:QI 1 "register_operand" "0")]
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UNSPEC_SWAP))]
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""
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"swap %0"
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[(set_attr "length" "1")
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(set_attr "cc" "none")])
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;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
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;; arithmetic shift left
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(define_insn "ashlqi3"
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(define_expand "ashlqi3"
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[(set (match_operand:QI 0 "register_operand" "")
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(ashift:QI (match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "general_operand" "")))]
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""
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"")
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(define_split ; ashlqi3_const4
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[(set (match_operand:QI 0 "d_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 4)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
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"")
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(define_split ; ashlqi3_const5
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[(set (match_operand:QI 0 "d_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 5)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
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"")
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(define_split ; ashlqi3_const6
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[(set (match_operand:QI 0 "d_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 6)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
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"")
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(define_insn "*ashlqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
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@ -1421,6 +1482,41 @@
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2 ; ashlqi3_l_const4
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[(set (match_operand:QI 0 "l_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 4)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 1) (const_int -16))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2 ; ashlqi3_l_const5
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[(set (match_operand:QI 0 "l_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 5)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
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(set (match_dup 1) (const_int -32))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2 ; ashlqi3_l_const6
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[(set (match_operand:QI 0 "l_register_operand" "")
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(ashift:QI (match_dup 0)
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(const_int 6)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
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(set (match_dup 1) (const_int -64))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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@ -1536,7 +1632,43 @@
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;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
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;; logical shift right
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(define_insn "lshrqi3"
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(define_expand "lshrqi3"
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[(set (match_operand:QI 0 "register_operand" "")
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(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "general_operand" "")))]
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""
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"")
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(define_split ; lshrqi3_const4
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[(set (match_operand:QI 0 "d_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 4)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
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"")
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(define_split ; lshrqi3_const5
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[(set (match_operand:QI 0 "d_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 5)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
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"")
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(define_split ; lshrqi3_const6
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[(set (match_operand:QI 0 "d_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 6)))]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
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(set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
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"")
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(define_insn "*lshrqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
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(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
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@ -1565,6 +1697,41 @@
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2 ; lshrqi3_l_const4
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[(set (match_operand:QI 0 "l_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 4)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 1) (const_int 15))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2 ; lshrqi3_l_const5
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[(set (match_operand:QI 0 "l_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 5)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
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(set (match_dup 1) (const_int 7))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2 ; lshrqi3_l_const6
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[(set (match_operand:QI 0 "l_register_operand" "")
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(lshiftrt:QI (match_dup 0)
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(const_int 6)))
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(match_scratch:QI 1 "d")]
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""
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[(set (match_dup 0) (unspec:QI [(match_dup 0)] UNSPEC_SWAP))
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(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
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(set (match_dup 1) (const_int 3))
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(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
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"")
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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