Move xx* builtins to vsx.md.
I noticed that the xx built-in functions (xxspltiw, xxspltidp, xxsplti32dx, xxeval, xxblend, and xxpermx) were all defined in altivec.md. However, since the XX instructions can take both traditional floating point and Altivec registers, these built-in functions should be in vsx.md. This patch just moves the insns from altivec.md to vsx.md. I also moved the VM3 mode iterator and VM3_char mode attribute from altivec.md to vsx.md, since the only use of these were for the XXBLEND insns. 2021-08-20 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md. (UNSPEC_XXSPLTIW): Move to vsx.md. (UNSPEC_XXSPLTID): Move to vsx.md. (UNSPEC_XXSPLTI32DX): Move to vsx.md. (UNSPEC_XXBLEND): Move to vsx.md. (UNSPEC_XXPERMX): Move to vsx.md. (VM3): Move to vsx.md. (VM3_char): Move to vsx.md. (xxspltiw_v4si): Move to vsx.md. (xxspltiw_v4sf): Move to vsx.md. (xxspltiw_v4sf_inst): Move to vsx.md. (xxspltidp_v2df): Move to vsx.md. (xxspltidp_v2df_inst): Move to vsx.md. (xxsplti32dx_v4si_inst): Move to vsx.md. (xxsplti32dx_v4sf): Move to vsx.md. (xxsplti32dx_v4sf_inst): Move to vsx.md. (xxblend_<mode>): Move to vsx.md. (xxpermx): Move to vsx.md. (xxpermx_inst): Move to vsx.md. * config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md. (UNSPEC_XXSPLTIW): Move from altivec.md. (UNSPEC_XXSPLTID): Move from altivec.md. (UNSPEC_XXSPLTI32DX): Move from altivec.md. (UNSPEC_XXBLEND): Move from altivec.md. (UNSPEC_XXPERMX): Move from altivec.md. (VM3): Move from altivec.md. (VM3_char): Move from altivec.md. (xxspltiw_v4si): Move from altivec.md. (xxspltiw_v4sf): Move from altivec.md. (xxspltiw_v4sf_inst): Move from altivec.md. (xxspltidp_v2df): Move from altivec.md. (xxspltidp_v2df_inst): Move from altivec.md. (xxsplti32dx_v4si_inst): Move from altivec.md. (xxsplti32dx_v4sf): Move from altivec.md. (xxsplti32dx_v4sf_inst): Move from altivec.md. (xxblend_<mode>): Move from altivec.md. (xxpermx): Move from altivec.md. (xxpermx_inst): Move from altivec.md.
This commit is contained in:
Michael Meissner
parent
b57fba5e37
commit
d2883be3c8
2 changed files with 206 additions and 197 deletions
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@ -175,16 +175,10 @@
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UNSPEC_VPEXTD
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UNSPEC_VCLRLB
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UNSPEC_VCLRRB
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UNSPEC_XXEVAL
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UNSPEC_VSTRIR
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UNSPEC_VSTRIL
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UNSPEC_SLDB
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UNSPEC_SRDB
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UNSPEC_XXSPLTIW
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UNSPEC_XXSPLTID
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UNSPEC_XXSPLTI32DX
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UNSPEC_XXBLEND
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UNSPEC_XXPERMX
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])
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(define_c_enum "unspecv"
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@ -225,21 +219,6 @@
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(KF "FLOAT128_VECTOR_P (KFmode)")
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(TF "FLOAT128_VECTOR_P (TFmode)")])
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;; Like VM2, just do char, short, int, long, float and double
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(define_mode_iterator VM3 [V4SI
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V8HI
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V16QI
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V4SF
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V2DF
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V2DI])
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(define_mode_attr VM3_char [(V2DI "d")
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(V4SI "w")
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(V8HI "h")
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(V16QI "b")
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(V2DF "d")
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(V4SF "w")])
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;; Map the Vector convert single precision to double precision for integer
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;; versus floating point
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(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
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@ -859,170 +838,6 @@
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"vs<SLDB_lr>dbi %0,%1,%2,%3"
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[(set_attr "type" "vecsimple")])
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(define_insn "xxspltiw_v4si"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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"xxspltiw %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxspltiw_v4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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{
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long value = rs6000_const_f32_to_i32 (operands[1]);
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emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
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DONE;
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})
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(define_insn "xxspltiw_v4sf_inst"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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"xxspltiw %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxspltidp_v2df"
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[(set (match_operand:V2DF 0 "register_operand" )
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(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
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UNSPEC_XXSPLTID))]
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"TARGET_POWER10"
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{
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long value = rs6000_const_f32_to_i32 (operands[1]);
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rs6000_emit_xxspltidp_v2df (operands[0], value);
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DONE;
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})
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(define_insn "xxspltidp_v2df_inst"
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[(set (match_operand:V2DF 0 "register_operand" "=wa")
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(unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
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UNSPEC_XXSPLTID))]
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"TARGET_POWER10"
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"xxspltidp %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxsplti32dx_v4si"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SI 3 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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{
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int index = INTVAL (operands[2]);
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if (!BYTES_BIG_ENDIAN)
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index = 1 - index;
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emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
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GEN_INT (index), operands[3]));
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DONE;
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}
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[(set_attr "type" "vecsimple")])
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(define_insn "xxsplti32dx_v4si_inst"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SI 3 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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"xxsplti32dx %x0,%2,%3"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxsplti32dx_v4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SF 3 "const_double_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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{
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int index = INTVAL (operands[2]);
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long value = rs6000_const_f32_to_i32 (operands[3]);
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if (!BYTES_BIG_ENDIAN)
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index = 1 - index;
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emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
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GEN_INT (index), GEN_INT (value)));
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DONE;
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})
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(define_insn "xxsplti32dx_v4sf_inst"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SI 3 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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"xxsplti32dx %x0,%2,%3"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_insn "xxblend_<mode>"
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[(set (match_operand:VM3 0 "register_operand" "=wa")
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(unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
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(match_operand:VM3 2 "register_operand" "wa")
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(match_operand:VM3 3 "register_operand" "wa")]
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UNSPEC_XXBLEND))]
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"TARGET_POWER10"
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"xxblendv<VM3_char> %x0,%x1,%x2,%x3"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxpermx"
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[(set (match_operand:V2DI 0 "register_operand" "+wa")
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(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
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(match_operand:V2DI 2 "register_operand" "wa")
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(match_operand:V16QI 3 "register_operand" "wa")
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(match_operand:QI 4 "u8bit_cint_operand" "n")]
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UNSPEC_XXPERMX))]
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"TARGET_POWER10"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_xxpermx_inst (operands[0], operands[1],
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operands[2], operands[3],
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operands[4]));
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else
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{
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/* Reverse value of byte element indexes by XORing with 0xFF.
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Reverse the 32-byte section identifier match by subracting bits [0:2]
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of elemet from 7. */
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int value = INTVAL (operands[4]);
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rtx vreg = gen_reg_rtx (V16QImode);
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emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
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emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
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value = 7 - value;
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emit_insn (gen_xxpermx_inst (operands[0], operands[2],
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operands[1], operands[3],
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GEN_INT (value)));
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}
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DONE;
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}
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[(set_attr "type" "vecsimple")])
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(define_insn "xxpermx_inst"
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[(set (match_operand:V2DI 0 "register_operand" "+v")
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(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
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(match_operand:V2DI 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")
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(match_operand:QI 4 "u3bit_cint_operand" "n")]
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UNSPEC_XXPERMX))]
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"TARGET_POWER10"
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"xxpermx %x0,%x1,%x2,%x3,%4"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "vstrir_<mode>"
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[(set (match_operand:VIshort 0 "altivec_register_operand")
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(unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
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@ -3873,18 +3688,6 @@
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[(set_attr "type" "vecperm")
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(set_attr "isa" "p9v,*")])
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(define_insn "xxeval"
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[(set (match_operand:V2DI 0 "register_operand" "=wa")
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(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
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(match_operand:V2DI 2 "register_operand" "wa")
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(match_operand:V2DI 3 "register_operand" "wa")
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(match_operand:QI 4 "u8bit_cint_operand" "n")]
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UNSPEC_XXEVAL))]
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"TARGET_POWER10"
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"xxeval %0,%1,%2,%3,%4"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "vec_unpacku_hi_v16qi"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
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@ -372,6 +372,12 @@
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UNSPEC_REPLACE_UN
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UNSPEC_VDIVES
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UNSPEC_VDIVEU
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UNSPEC_XXEVAL
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UNSPEC_XXSPLTIW
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UNSPEC_XXSPLTID
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UNSPEC_XXSPLTI32DX
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UNSPEC_XXBLEND
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UNSPEC_XXPERMX
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])
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(define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
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@ -392,6 +398,22 @@
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(define_mode_attr REPLACE_ELT_max [(V4SI "12") (V4SF "12")
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(V2DI "8") (V2DF "8")])
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;; Like VM2 in altivec.md, just do char, short, int, long, float and double
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(define_mode_iterator VM3 [V4SI
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V8HI
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V16QI
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V4SF
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V2DF
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V2DI])
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(define_mode_attr VM3_char [(V2DI "d")
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(V4SI "w")
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(V8HI "h")
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(V16QI "b")
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(V2DF "d")
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(V4SF "w")])
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;; VSX moves
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;; The patterns for LE permuted loads and stores come before the general
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@ -6383,3 +6405,187 @@
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"TARGET_POWER10"
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"vmulld %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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;; XXSPLTIW built-in function support
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(define_insn "xxspltiw_v4si"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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"xxspltiw %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxspltiw_v4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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{
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long value = rs6000_const_f32_to_i32 (operands[1]);
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emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
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DONE;
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})
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(define_insn "xxspltiw_v4sf_inst"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
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UNSPEC_XXSPLTIW))]
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"TARGET_POWER10"
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"xxspltiw %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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;; XXSPLTIDP built-in function support
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(define_expand "xxspltidp_v2df"
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[(set (match_operand:V2DF 0 "register_operand" )
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(unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
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UNSPEC_XXSPLTID))]
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"TARGET_POWER10"
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{
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long value = rs6000_const_f32_to_i32 (operands[1]);
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rs6000_emit_xxspltidp_v2df (operands[0], value);
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DONE;
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})
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(define_insn "xxspltidp_v2df_inst"
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[(set (match_operand:V2DF 0 "register_operand" "=wa")
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(unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
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UNSPEC_XXSPLTID))]
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"TARGET_POWER10"
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"xxspltidp %x0,%1"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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;; XXSPLTI32DX built-in function support
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(define_expand "xxsplti32dx_v4si"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SI 3 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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{
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int index = INTVAL (operands[2]);
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if (!BYTES_BIG_ENDIAN)
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index = 1 - index;
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emit_insn (gen_xxsplti32dx_v4si_inst (operands[0], operands[1],
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GEN_INT (index), operands[3]));
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DONE;
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}
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[(set_attr "type" "vecsimple")])
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(define_insn "xxsplti32dx_v4si_inst"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
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(match_operand:QI 2 "u1bit_cint_operand" "n")
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(match_operand:SI 3 "s32bit_cint_operand" "n")]
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UNSPEC_XXSPLTI32DX))]
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"TARGET_POWER10"
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"xxsplti32dx %x0,%2,%3"
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[(set_attr "type" "vecsimple")
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(set_attr "prefixed" "yes")])
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(define_expand "xxsplti32dx_v4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=wa")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
|
||||
(match_operand:QI 2 "u1bit_cint_operand" "n")
|
||||
(match_operand:SF 3 "const_double_operand" "n")]
|
||||
UNSPEC_XXSPLTI32DX))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
int index = INTVAL (operands[2]);
|
||||
long value = rs6000_const_f32_to_i32 (operands[3]);
|
||||
if (!BYTES_BIG_ENDIAN)
|
||||
index = 1 - index;
|
||||
|
||||
emit_insn (gen_xxsplti32dx_v4sf_inst (operands[0], operands[1],
|
||||
GEN_INT (index), GEN_INT (value)));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "xxsplti32dx_v4sf_inst"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=wa")
|
||||
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
|
||||
(match_operand:QI 2 "u1bit_cint_operand" "n")
|
||||
(match_operand:SI 3 "s32bit_cint_operand" "n")]
|
||||
UNSPEC_XXSPLTI32DX))]
|
||||
"TARGET_POWER10"
|
||||
"xxsplti32dx %x0,%2,%3"
|
||||
[(set_attr "type" "vecsimple")
|
||||
(set_attr "prefixed" "yes")])
|
||||
|
||||
;; XXBLEND built-in function support
|
||||
(define_insn "xxblend_<mode>"
|
||||
[(set (match_operand:VM3 0 "register_operand" "=wa")
|
||||
(unspec:VM3 [(match_operand:VM3 1 "register_operand" "wa")
|
||||
(match_operand:VM3 2 "register_operand" "wa")
|
||||
(match_operand:VM3 3 "register_operand" "wa")]
|
||||
UNSPEC_XXBLEND))]
|
||||
"TARGET_POWER10"
|
||||
"xxblendv<VM3_char> %x0,%x1,%x2,%x3"
|
||||
[(set_attr "type" "vecsimple")
|
||||
(set_attr "prefixed" "yes")])
|
||||
|
||||
;; XXPERMX built-in function support
|
||||
(define_expand "xxpermx"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "+wa")
|
||||
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
|
||||
(match_operand:V2DI 2 "register_operand" "wa")
|
||||
(match_operand:V16QI 3 "register_operand" "wa")
|
||||
(match_operand:QI 4 "u8bit_cint_operand" "n")]
|
||||
UNSPEC_XXPERMX))]
|
||||
"TARGET_POWER10"
|
||||
{
|
||||
if (BYTES_BIG_ENDIAN)
|
||||
emit_insn (gen_xxpermx_inst (operands[0], operands[1],
|
||||
operands[2], operands[3],
|
||||
operands[4]));
|
||||
else
|
||||
{
|
||||
/* Reverse value of byte element indexes by XORing with 0xFF.
|
||||
Reverse the 32-byte section identifier match by subracting bits [0:2]
|
||||
of elemet from 7. */
|
||||
int value = INTVAL (operands[4]);
|
||||
rtx vreg = gen_reg_rtx (V16QImode);
|
||||
|
||||
emit_insn (gen_xxspltib_v16qi (vreg, GEN_INT (-1)));
|
||||
emit_insn (gen_xorv16qi3 (operands[3], operands[3], vreg));
|
||||
value = 7 - value;
|
||||
emit_insn (gen_xxpermx_inst (operands[0], operands[2],
|
||||
operands[1], operands[3],
|
||||
GEN_INT (value)));
|
||||
}
|
||||
|
||||
DONE;
|
||||
}
|
||||
[(set_attr "type" "vecsimple")])
|
||||
|
||||
(define_insn "xxpermx_inst"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "+v")
|
||||
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
|
||||
(match_operand:V2DI 2 "register_operand" "v")
|
||||
(match_operand:V16QI 3 "register_operand" "v")
|
||||
(match_operand:QI 4 "u3bit_cint_operand" "n")]
|
||||
UNSPEC_XXPERMX))]
|
||||
"TARGET_POWER10"
|
||||
"xxpermx %x0,%x1,%x2,%x3,%4"
|
||||
[(set_attr "type" "vecsimple")
|
||||
(set_attr "prefixed" "yes")])
|
||||
|
||||
;; XXEVAL built-in function support
|
||||
(define_insn "xxeval"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=wa")
|
||||
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "wa")
|
||||
(match_operand:V2DI 2 "register_operand" "wa")
|
||||
(match_operand:V2DI 3 "register_operand" "wa")
|
||||
(match_operand:QI 4 "u8bit_cint_operand" "n")]
|
||||
UNSPEC_XXEVAL))]
|
||||
"TARGET_POWER10"
|
||||
"xxeval %0,%1,%2,%3,%4"
|
||||
[(set_attr "type" "vecsimple")
|
||||
(set_attr "prefixed" "yes")])
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue