s390.c (s390_swap_cmp): New function.
2008-12-15 Wolfgang Gellerich <gellerich@de.ibm.com> * config/s390/s390.c (s390_swap_cmp): New function. (s390_non_addr_reg_read_p): New function. (s390_z10_optimize_cmp): New function. (s390_reorg): Added call to s390_optimize_cmp. * config/s390/s390.md (nop1): New insn. From-SVN: r142762
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Wolfgang Gellerich
Andreas Krebbel
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3 changed files with 117 additions and 0 deletions
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@ -1,3 +1,11 @@
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2008-12-15 Wolfgang Gellerich <gellerich@de.ibm.com>
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* config/s390/s390.c (s390_swap_cmp): New function.
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(s390_non_addr_reg_read_p): New function.
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(s390_z10_optimize_cmp): New function.
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(s390_reorg): Added call to s390_optimize_cmp.
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* config/s390/s390.md (nop1): New insn.
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2008-12-12 Rainer Emrich <r.emrich@de.tecosim.com>
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2008-12-12 Rainer Emrich <r.emrich@de.tecosim.com>
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PR bootstrap/38383
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PR bootstrap/38383
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@ -9589,6 +9589,104 @@ s390_optimize_prologue (void)
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}
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}
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}
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}
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/* Exchange the two operands of COND, and swap its mask so that the
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semantics does not change. */
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static void
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s390_swap_cmp (rtx cond)
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{
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enum rtx_code code = swap_condition (GET_CODE (cond));
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rtx tmp = XEXP (cond, 0);
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XEXP (cond, 0) = XEXP (cond, 1);
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XEXP (cond, 1) = tmp;
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PUT_CODE (cond, code);
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}
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/* Returns 1 if INSN reads the value of REG for purposes not related
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to addressing of memory, and 0 otherwise. */
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static int
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s390_non_addr_reg_read_p (rtx reg, rtx insn)
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{
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return reg_referenced_p (reg, PATTERN (insn))
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&& !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
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}
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/* On z10, instructions of the compare-and-branch family have the
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property to access the register occurring as second operand with
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its bits complemented. If such a compare is grouped with a second
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instruction that accesses the same register non-complemented, and
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if that register's value is delivered via a bypass, then the
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pipeline recycles, thereby causing significant performance decline.
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This function locates such situations and exchanges the two
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operands of the compare. */
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static void
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s390_z10_optimize_cmp (void)
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{
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rtx insn, prev_insn, next_insn;
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int added_NOPs = 0;
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
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continue;
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if (get_attr_z10prop (insn) == Z10PROP_Z10_COBRA)
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{
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rtx op0, op1, pattern, jump_expr, cond;
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/* Extract the comparison´s condition and its operands. */
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pattern = single_set (insn);
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gcc_assert (GET_CODE (pattern) == SET);
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jump_expr = XEXP (pattern, 1);
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gcc_assert (GET_CODE (jump_expr) == IF_THEN_ELSE);
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cond = XEXP (jump_expr, 0);
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op0 = XEXP (cond, 0);
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op1 = XEXP (cond, 1);
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/* Swap the COMPARE´s arguments and its mask if there is a
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conflicting access in the previous insn. */
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prev_insn = PREV_INSN (insn);
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if (prev_insn != NULL_RTX && INSN_P (prev_insn)
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&& reg_referenced_p (op1, PATTERN (prev_insn)))
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{
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s390_swap_cmp (cond);
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op0 = XEXP (cond, 0);
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op1 = XEXP (cond, 1);
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}
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/* Check if there is a conflict with the next insn. If there
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was no conflict with the previous insn, then swap the
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COMPARE´s arguments and its mask. If we already swapped
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the operands, or if swapping them would cause a conflict
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with the previous insn, issue a NOP after the COMPARE in
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order to separate the two instuctions. */
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next_insn = NEXT_INSN (insn);
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if (next_insn != NULL_RTX && INSN_P (next_insn)
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&& s390_non_addr_reg_read_p (op1, next_insn))
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{
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if (s390_non_addr_reg_read_p (op0, prev_insn))
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{
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if (REGNO(op1) == 0)
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emit_insn_after (gen_nop1 (), insn);
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else
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emit_insn_after (gen_nop (), insn);
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added_NOPs = 1;
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}
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else
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s390_swap_cmp (cond);
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}
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}
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}
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/* Adjust branches if we added new instructions. */
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if (added_NOPs)
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shorten_branches (get_insns ());
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}
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/* Perform machine-dependent processing. */
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/* Perform machine-dependent processing. */
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static void
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static void
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@ -9698,6 +9796,11 @@ s390_reorg (void)
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/* Try to optimize prologue and epilogue further. */
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/* Try to optimize prologue and epilogue further. */
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s390_optimize_prologue ();
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s390_optimize_prologue ();
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/* Eliminate z10-specific pipeline recycles related to some compare
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instructions. */
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if (TARGET_Z10)
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s390_z10_optimize_cmp ();
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}
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}
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@ -8467,6 +8467,12 @@
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"lr\t0,0"
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"lr\t0,0"
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[(set_attr "op_type" "RR")])
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[(set_attr "op_type" "RR")])
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(define_insn "nop1"
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[(const_int 1)]
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""
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"lr\t1,1"
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[(set_attr "op_type" "RR")])
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;
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;
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; Special literal pool access instruction pattern(s).
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; Special literal pool access instruction pattern(s).
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