i386.md (iptrsize): New mode attribute.
* config/i386/i386.md (iptrsize): New mode attribute.
(tp_seg): Ditto.
(*load_tp_<mode>): Macroize insn from *load_tp_{si,di} using P
mode iterator.
(*add_tp_<mode>): Ditto from *add_tp_{si,di}.
(stack_protect_set_<mode>): Ditto from stack_protect_set_{si,di}.
(stack_protect_test_<mode>): Ditto from stack_protect_test_{si,di}.
(stack_tls_protect_set_<mode>): Ditto from
stack_tls_protect_set_{si,di}. Use %@ to output segment register
of thread base pointer load.
(stack_tls_protect_test_<mode>): Ditto from
stack_tls_protect_test_{si,di}. Use %@ to output segment register
of thread base pointer load.
(stack_protect_set): Rewrite using indirect functions.
(stack_protect_test): Ditto.
* config/i386/i386.c (ix86_print_operand_punct_valid): Add '@'.
(ix86_print_operand): Handle '@'.
From-SVN: r163900
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
195a95c430
commit
d1e74401c1
3 changed files with 100 additions and 135 deletions
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@ -1,3 +1,23 @@
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2010-09-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (iptrsize): New mode attribute.
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(tp_seg): Ditto.
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(*load_tp_<mode>): Macroize insn from *load_tp_{si,di} using P
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mode iterator.
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(*add_tp_<mode>): Ditto from *add_tp_{si,di}.
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(stack_protect_set_<mode>): Ditto from stack_protect_set_{si,di}.
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(stack_protect_test_<mode>): Ditto from stack_protect_test_{si,di}.
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(stack_tls_protect_set_<mode>): Ditto from
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stack_tls_protect_set_{si,di}. Use %@ to output segment register
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of thread base pointer load.
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(stack_tls_protect_test_<mode>): Ditto from
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stack_tls_protect_test_{si,di}. Use %@ to output segment register
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of thread base pointer load.
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(stack_protect_set): Rewrite using indirect functions.
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(stack_protect_test): Ditto.
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* config/i386/i386.c (ix86_print_operand_punct_valid): Add '@'.
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(ix86_print_operand): Handle '@'.
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2010-09-05 Giuseppe Scrivano <gscrivano@gnu.org>
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* tree-tailcall.c (process_assignment): Handle NEGATE_EXPR and
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@ -12404,6 +12404,7 @@ get_some_local_dynamic_name (void)
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Y -- print condition for XOP pcom* instruction.
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+ -- print a branch hint as 'cs' or 'ds' prefix
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; -- print a semicolon (after prefixes due to bug in older gas).
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@ -- print a segment register of thread base pointer load
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*/
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void
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@ -12882,6 +12883,19 @@ ix86_print_operand (FILE *file, rtx x, int code)
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#endif
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return;
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case '@':
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('%', file);
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/* The kernel uses a different segment register for performance
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reasons; a system call would not have to trash the userspace
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segment register, which would be expensive. */
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if (TARGET_64BIT && ix86_cmodel != CM_KERNEL)
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fputs ("fs", file);
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else
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fputs ("gs", file);
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return;
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default:
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output_operand_lossage ("invalid operand code '%c'", code);
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}
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@ -13012,7 +13026,8 @@ ix86_print_operand (FILE *file, rtx x, int code)
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static bool
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ix86_print_operand_punct_valid_p (unsigned char code)
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{
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return (code == '*' || code == '+' || code == '&' || code == ';');
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return (code == '@' || code == '*' || code == '+'
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|| code == '&' || code == ';');
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}
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/* Print a memory operand whose address is ADDR. */
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@ -59,6 +59,7 @@
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;; Y -- print condition for XOP pcom* instruction.
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;; + -- print a branch hint as 'cs' or 'ds' prefix
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;; ; -- print a semicolon (after prefixes due to bug in older gas).
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;; @ -- print a segment register of thread base pointer load
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;; UNSPEC usage:
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@ -821,6 +822,12 @@
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;; Instruction suffix for integer modes.
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(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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;; Pointer size prefix for integer modes (Intel asm dialect)
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(define_mode_attr iptrsize [(QI "BYTE")
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(HI "WORD")
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(SI "DWORD")
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(DI "QWORD")])
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;; Register class for integer modes.
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(define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
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@ -12042,50 +12049,28 @@
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(clobber (reg:CC FLAGS_REG))])]
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"")
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;; Segment register for the thread base ptr load
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(define_mode_attr tp_seg [(SI "gs") (DI "fs")])
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;; Load and add the thread base pointer from %gs:0.
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(define_insn "*load_tp_si"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const_int 0)] UNSPEC_TP))]
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"!TARGET_64BIT"
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"mov{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
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(define_insn "*load_tp_<mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec:P [(const_int 0)] UNSPEC_TP))]
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""
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"mov{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
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(set_attr "memory" "load")
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(set_attr "imm_disp" "false")])
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(define_insn "*add_tp_si"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
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(match_operand:SI 1 "register_operand" "0")))
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(define_insn "*add_tp_<mode>"
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[(set (match_operand:P 0 "register_operand" "=r")
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(plus:P (unspec:P [(const_int 0)] UNSPEC_TP)
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(match_operand:P 1 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT"
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"add{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
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[(set_attr "type" "alu")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
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(set_attr "memory" "load")
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(set_attr "imm_disp" "false")])
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(define_insn "*load_tp_di"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_TP))]
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"TARGET_64BIT"
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"mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
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(set_attr "memory" "load")
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(set_attr "imm_disp" "false")])
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(define_insn "*add_tp_di"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
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(match_operand:DI 1 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"add{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
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""
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"add{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
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[(set_attr "type" "alu")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
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@ -12219,8 +12204,6 @@
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operands[4] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
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emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
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})
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;;
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;; These patterns match the binary 387 instructions for addM3, subM3,
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;; mulM3 and divM3. There are three patterns for each of DFmode and
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@ -17344,66 +17327,40 @@
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(match_operand 1 "memory_operand" "")]
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""
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{
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rtx (*insn)(rtx, rtx);
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#ifdef TARGET_THREAD_SSP_OFFSET
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if (TARGET_64BIT)
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emit_insn (gen_stack_tls_protect_set_di (operands[0],
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GEN_INT (TARGET_THREAD_SSP_OFFSET)));
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else
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emit_insn (gen_stack_tls_protect_set_si (operands[0],
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GEN_INT (TARGET_THREAD_SSP_OFFSET)));
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operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
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insn = (TARGET_64BIT
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? gen_stack_tls_protect_set_di
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: gen_stack_tls_protect_set_si);
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#else
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if (TARGET_64BIT)
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emit_insn (gen_stack_protect_set_di (operands[0], operands[1]));
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else
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emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
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insn = (TARGET_64BIT
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? gen_stack_protect_set_di
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: gen_stack_protect_set_si);
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#endif
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emit_insn (insn (operands[0], operands[1]));
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DONE;
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})
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(define_insn "stack_protect_set_si"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
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(set (match_scratch:SI 2 "=&r") (const_int 0))
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(define_insn "stack_protect_set_<mode>"
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[(set (match_operand:P 0 "memory_operand" "=m")
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(unspec:P [(match_operand:P 1 "memory_operand" "m")] UNSPEC_SP_SET))
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(set (match_scratch:P 2 "=&r") (const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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"mov{l}\t{%1, %2|%2, %1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
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"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
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[(set_attr "type" "multi")])
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(define_insn "stack_protect_set_di"
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[(set (match_operand:DI 0 "memory_operand" "=m")
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(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
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(set (match_scratch:DI 2 "=&r") (const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"mov{q}\t{%1, %2|%2, %1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
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[(set_attr "type" "multi")])
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(define_insn "stack_tls_protect_set_si"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(unspec:SI [(match_operand:SI 1 "const_int_operand" "i")]
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UNSPEC_SP_TLS_SET))
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(set (match_scratch:SI 2 "=&r") (const_int 0))
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(define_insn "stack_tls_protect_set_<mode>"
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[(set (match_operand:P 0 "memory_operand" "=m")
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(unspec:P [(match_operand:P 1 "const_int_operand" "i")]
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UNSPEC_SP_TLS_SET))
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(set (match_scratch:P 2 "=&r") (const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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"mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
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[(set_attr "type" "multi")])
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(define_insn "stack_tls_protect_set_di"
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[(set (match_operand:DI 0 "memory_operand" "=m")
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(unspec:DI [(match_operand:DI 1 "const_int_operand" "i")]
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UNSPEC_SP_TLS_SET))
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(set (match_scratch:DI 2 "=&r") (const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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{
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/* The kernel uses a different segment register for performance reasons; a
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system call would not have to trash the userspace segment register,
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which would be expensive */
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if (ix86_cmodel != CM_KERNEL)
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return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
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else
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return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
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}
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"mov{<imodesuffix>}\t{%@:%P1, %2|%2, <iptrsize> PTR %@:%P1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
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[(set_attr "type" "multi")])
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(define_expand "stack_protect_test"
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@ -17414,71 +17371,44 @@
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{
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rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
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rtx (*insn)(rtx, rtx, rtx);
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#ifdef TARGET_THREAD_SSP_OFFSET
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if (TARGET_64BIT)
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emit_insn (gen_stack_tls_protect_test_di (flags, operands[0],
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GEN_INT (TARGET_THREAD_SSP_OFFSET)));
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else
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emit_insn (gen_stack_tls_protect_test_si (flags, operands[0],
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GEN_INT (TARGET_THREAD_SSP_OFFSET)));
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operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
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insn = (TARGET_64BIT
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? gen_stack_tls_protect_test_di
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: gen_stack_tls_protect_test_si);
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#else
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if (TARGET_64BIT)
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emit_insn (gen_stack_protect_test_di (flags, operands[0], operands[1]));
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else
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emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
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insn = (TARGET_64BIT
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? gen_stack_protect_test_di
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: gen_stack_protect_test_si);
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#endif
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emit_insn (insn (flags, operands[0], operands[1]));
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emit_jump_insn (gen_cbranchcc4 (gen_rtx_EQ (VOIDmode, flags, const0_rtx),
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flags, const0_rtx, operands[2]));
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DONE;
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})
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(define_insn "stack_protect_test_si"
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(define_insn "stack_protect_test_<mode>"
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[(set (match_operand:CCZ 0 "flags_reg_operand" "")
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(unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
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(match_operand:SI 2 "memory_operand" "m")]
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(unspec:CCZ [(match_operand:P 1 "memory_operand" "m")
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(match_operand:P 2 "memory_operand" "m")]
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UNSPEC_SP_TEST))
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(clobber (match_scratch:SI 3 "=&r"))]
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(clobber (match_scratch:P 3 "=&r"))]
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""
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"mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%2, %3|%3, %2}"
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"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
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[(set_attr "type" "multi")])
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(define_insn "stack_protect_test_di"
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(define_insn "stack_tls_protect_test_<mode>"
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[(set (match_operand:CCZ 0 "flags_reg_operand" "")
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(unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
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(match_operand:DI 2 "memory_operand" "m")]
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UNSPEC_SP_TEST))
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(clobber (match_scratch:DI 3 "=&r"))]
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"TARGET_64BIT"
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"mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%2, %3|%3, %2}"
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[(set_attr "type" "multi")])
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(define_insn "stack_tls_protect_test_si"
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[(set (match_operand:CCZ 0 "flags_reg_operand" "")
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(unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
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(match_operand:SI 2 "const_int_operand" "i")]
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(unspec:CCZ [(match_operand:P 1 "memory_operand" "m")
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(match_operand:P 2 "const_int_operand" "i")]
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UNSPEC_SP_TLS_TEST))
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(clobber (match_scratch:SI 3 "=r"))]
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(clobber (match_scratch:P 3 "=r"))]
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""
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"mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR gs:%P2}"
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[(set_attr "type" "multi")])
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(define_insn "stack_tls_protect_test_di"
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[(set (match_operand:CCZ 0 "flags_reg_operand" "")
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(unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
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(match_operand:DI 2 "const_int_operand" "i")]
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UNSPEC_SP_TLS_TEST))
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(clobber (match_scratch:DI 3 "=r"))]
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"TARGET_64BIT"
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{
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/* The kernel uses a different segment register for performance reasons; a
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system call would not have to trash the userspace segment register,
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which would be expensive */
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if (ix86_cmodel != CM_KERNEL)
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return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR fs:%P2}";
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else
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return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR gs:%P2}";
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}
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"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%@:%P2, %3|%3, <iptrsize> PTR %@:%P2}"
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[(set_attr "type" "multi")])
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(define_insn "sse4_2_crc32<mode>"
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||||
|
|
|
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