rs6000-builtin.def (ST_ELEMREV_V1TI, [...]): Add macro expansion.
gcc/ChangeLog: 2018-01-22 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (ST_ELEMREV_V1TI, LD_ELEMREV_V1TI, LVX_V1TI): Add macro expansion. * config/rs6000/rs6000-c.c (altivec_builtin_types): Add argument definitions for VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_VEC_ST, VSX_BUILTIN_VEC_XL, LD_ELEMREV_V1TI builtins. * config/rs6000/rs6000-p8swap.c (insn_is_swappable_p); Change check to determine if the instruction is a byte reversing entry. Fix typo in comment. * config/rs6000/rs6000.c (altivec_expand_builtin): Add case entry for VSX_BUILTIN_ST_ELEMREV_V1TI and VSX_BUILTIN_LD_ELEMREV_V1TI. Add def_builtin calls for new builtins. * config/rs6000/vsx.md (vsx_st_elemrev_v1ti, vsx_ld_elemrev_v1ti): Add define_insn expansion. gcc/testsuite/ChangeLog: 2018-01-22 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/powerpc.exp: Add torture tests for builtins-4-runnable.c, builtins-6-runnable.c, builtins-5-p9-runnable.c, builtins-6-p9-runnable.c. * gcc.target/powerpc/builtins-6-runnable.c: New test file. * gcc.target/powerpc/builtins-4-runnable.c: Add additional tests for signed/unsigned 128-bit and long long int loads. From-SVN: r256952
This commit is contained in:
Carl Love
Carl Love
parent
f25d7e06e2
commit
d10cff958f
10 changed files with 1605 additions and 35 deletions
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@ -1,3 +1,19 @@
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2018-01-22 Carl Love <cel@us.ibm.com>
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* config/rs6000/rs6000-builtin.def (ST_ELEMREV_V1TI, LD_ELEMREV_V1TI,
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LVX_V1TI): Add macro expansion.
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* config/rs6000/rs6000-c.c (altivec_builtin_types): Add argument
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definitions for VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_VEC_ST,
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VSX_BUILTIN_VEC_XL, LD_ELEMREV_V1TI builtins.
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* config/rs6000/rs6000-p8swap.c (insn_is_swappable_p);
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Change check to determine if the instruction is a byte reversing
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entry. Fix typo in comment.
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* config/rs6000/rs6000.c (altivec_expand_builtin): Add case entry
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for VSX_BUILTIN_ST_ELEMREV_V1TI and VSX_BUILTIN_LD_ELEMREV_V1TI.
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Add def_builtin calls for new builtins.
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* config/rs6000/vsx.md (vsx_st_elemrev_v1ti, vsx_ld_elemrev_v1ti):
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Add define_insn expansion.
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2018-01-22 Sebastian Perta <sebastian.perta@renesas.com>
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* config/rl78/rl78.md: New define_expand "umaxdi3".
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@ -1242,6 +1242,7 @@ BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM)
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BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM)
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BU_ALTIVEC_X (LVX, "lvx", MEM)
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BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM)
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BU_ALTIVEC_X (LVX_V1TI, "lvx_v1ti", MEM)
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BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM)
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BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM)
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BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM)
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@ -1792,12 +1793,14 @@ BU_VSX_X (STXVW4X_V4SF, "stxvw4x_v4sf", MEM)
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BU_VSX_X (STXVW4X_V4SI, "stxvw4x_v4si", MEM)
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BU_VSX_X (STXVW4X_V8HI, "stxvw4x_v8hi", MEM)
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BU_VSX_X (STXVW4X_V16QI, "stxvw4x_v16qi", MEM)
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BU_VSX_X (LD_ELEMREV_V1TI, "ld_elemrev_v1ti", MEM)
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BU_VSX_X (LD_ELEMREV_V2DF, "ld_elemrev_v2df", MEM)
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BU_VSX_X (LD_ELEMREV_V2DI, "ld_elemrev_v2di", MEM)
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BU_VSX_X (LD_ELEMREV_V4SF, "ld_elemrev_v4sf", MEM)
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BU_VSX_X (LD_ELEMREV_V4SI, "ld_elemrev_v4si", MEM)
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BU_VSX_X (LD_ELEMREV_V8HI, "ld_elemrev_v8hi", MEM)
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BU_VSX_X (LD_ELEMREV_V16QI, "ld_elemrev_v16qi", MEM)
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BU_VSX_X (ST_ELEMREV_V1TI, "st_elemrev_v1ti", MEM)
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BU_VSX_X (ST_ELEMREV_V2DF, "st_elemrev_v2df", MEM)
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BU_VSX_X (ST_ELEMREV_V2DI, "st_elemrev_v2di", MEM)
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BU_VSX_X (ST_ELEMREV_V4SF, "st_elemrev_v4sf", MEM)
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@ -3162,16 +3162,27 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
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RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
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RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
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~RS6000_BTI_unsigned_V2DI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
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~RS6000_BTI_unsigned_long_long, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
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RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
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{ VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
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@ -3206,6 +3217,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
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{ VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
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{ VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
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RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
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{ VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
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{ VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
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{ VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
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@ -4089,6 +4104,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
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{ VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
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RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
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{ VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
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RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
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{ VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
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RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
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{ VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
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RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
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{ VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
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@ -4189,9 +4208,19 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
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~RS6000_BTI_unsigned_V2DI, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
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{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
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@ -4243,6 +4272,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
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RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
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RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
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~RS6000_BTI_long_long },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
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RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
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~RS6000_BTI_unsigned_long_long },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
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RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
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RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
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RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
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{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
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@ -873,10 +873,11 @@ insn_is_swappable_p (swap_web_entry *insn_entry, rtx insn,
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if (insn_entry[i].is_store)
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{
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if (GET_CODE (body) == SET
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&& GET_CODE (SET_SRC (body)) != UNSPEC)
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&& GET_CODE (SET_SRC (body)) != UNSPEC
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&& GET_CODE (SET_SRC (body)) != VEC_SELECT)
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{
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rtx lhs = SET_DEST (body);
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/* Even without a swap, the LHS might be a vec_select for, say,
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/* Even without a swap, the RHS might be a vec_select for, say,
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a byte-reversing store. */
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if (GET_CODE (lhs) != MEM)
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return 0;
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@ -15582,6 +15582,12 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
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unaligned-supporting store, so use a generic expander. For
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little-endian, the exact element-reversing instruction must
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be used. */
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case VSX_BUILTIN_ST_ELEMREV_V1TI:
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{
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enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
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: CODE_FOR_vsx_st_elemrev_v1ti);
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return altivec_expand_stv_builtin (code, exp);
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}
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case VSX_BUILTIN_ST_ELEMREV_V2DF:
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{
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enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
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@ -15856,6 +15862,12 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
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: CODE_FOR_vsx_ld_elemrev_v2df);
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return altivec_expand_lv_builtin (code, exp, target, false);
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}
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case VSX_BUILTIN_LD_ELEMREV_V1TI:
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{
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enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
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: CODE_FOR_vsx_ld_elemrev_v1ti);
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return altivec_expand_lv_builtin (code, exp, target, false);
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}
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case VSX_BUILTIN_LD_ELEMREV_V2DI:
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{
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enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
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@ -17457,6 +17469,10 @@ altivec_init_builtins (void)
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= build_function_type_list (void_type_node,
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V2DF_type_node, long_integer_type_node,
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pvoid_type_node, NULL_TREE);
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tree void_ftype_v1ti_long_pvoid
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= build_function_type_list (void_type_node,
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V1TI_type_node, long_integer_type_node,
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pvoid_type_node, NULL_TREE);
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tree void_ftype_v2di_long_pvoid
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= build_function_type_list (void_type_node,
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V2DI_type_node, long_integer_type_node,
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@ -17612,6 +17628,8 @@ altivec_init_builtins (void)
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VSX_BUILTIN_LD_ELEMREV_V16QI);
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def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
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VSX_BUILTIN_ST_ELEMREV_V2DF);
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def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
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VSX_BUILTIN_ST_ELEMREV_V1TI);
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def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
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VSX_BUILTIN_ST_ELEMREV_V2DI);
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def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
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@ -17935,6 +17953,8 @@ altivec_init_builtins (void)
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= build_function_type_list (void_type_node,
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V1TI_type_node, long_integer_type_node,
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pvoid_type_node, NULL_TREE);
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def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
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VSX_BUILTIN_LD_ELEMREV_V1TI);
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def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
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VSX_BUILTIN_LXVD2X_V1TI);
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def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
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@ -1302,6 +1302,17 @@
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"lxvd2x %x0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "vsx_ld_elemrev_v1ti"
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[(set (match_operand:V1TI 0 "vsx_register_operand" "=wa")
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(vec_select:V1TI
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(match_operand:V1TI 1 "memory_operand" "Z")
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(parallel [(const_int 0)])))]
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"VECTOR_MEM_VSX_P (V1TImode) && !BYTES_BIG_ENDIAN"
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{
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return "lxvd2x %x0,%y1\;xxpermdi %x0,%x0,%x0,2";
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}
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[(set_attr "type" "vecload")])
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(define_insn "vsx_ld_elemrev_v2df"
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[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
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(vec_select:V2DF
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@ -1431,6 +1442,18 @@
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"lxvb16x %x0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "vsx_st_elemrev_v1ti"
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[(set (match_operand:V1TI 0 "memory_operand" "=Z")
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(vec_select:V1TI
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(match_operand:V1TI 1 "vsx_register_operand" "+wa")
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(parallel [(const_int 0)])))
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(clobber (match_dup 1))]
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"VECTOR_MEM_VSX_P (V2DImode) && !BYTES_BIG_ENDIAN"
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{
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return "xxpermdi %x1,%x1,%x1,2\;stxvd2x %x1,%y0";
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}
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[(set_attr "type" "vecstore")])
|
||||
|
||||
(define_insn "vsx_st_elemrev_v2df"
|
||||
[(set (match_operand:V2DF 0 "memory_operand" "=Z")
|
||||
(vec_select:V2DF
|
||||
|
|
@ -1481,7 +1504,7 @@
|
|||
{
|
||||
if (!TARGET_P9_VECTOR)
|
||||
{
|
||||
rtx subreg, perm[16], pcv;
|
||||
rtx mem_subreg, subreg, perm[16], pcv;
|
||||
rtx tmp = gen_reg_rtx (V8HImode);
|
||||
/* 2 is leftmost element in register */
|
||||
unsigned int reorder[16] = {13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2};
|
||||
|
|
@ -1496,11 +1519,21 @@
|
|||
emit_insn (gen_altivec_vperm_v8hi_direct (tmp, operands[1],
|
||||
operands[1], pcv));
|
||||
subreg = simplify_gen_subreg (V4SImode, tmp, V8HImode, 0);
|
||||
emit_insn (gen_vsx_st_elemrev_v4si (subreg, operands[0]));
|
||||
mem_subreg = simplify_gen_subreg (V4SImode, operands[0], V8HImode, 0);
|
||||
emit_insn (gen_vsx_st_elemrev_v4si (mem_subreg, subreg));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
(define_insn "*vsx_st_elemrev_v2di_internal"
|
||||
[(set (match_operand:V2DI 0 "memory_operand" "=Z")
|
||||
(vec_select:V2DI
|
||||
(match_operand:V2DI 1 "vsx_register_operand" "wa")
|
||||
(parallel [(const_int 1) (const_int 0)])))]
|
||||
"VECTOR_MEM_VSX_P (V2DImode) && !BYTES_BIG_ENDIAN && TARGET_P9_VECTOR"
|
||||
"stxvd2x %x1,%y0"
|
||||
[(set_attr "type" "vecstore")])
|
||||
|
||||
(define_insn "*vsx_st_elemrev_v8hi_internal"
|
||||
[(set (match_operand:V8HI 0 "memory_operand" "=Z")
|
||||
(vec_select:V8HI
|
||||
|
|
@ -1529,7 +1562,7 @@
|
|||
{
|
||||
if (!TARGET_P9_VECTOR)
|
||||
{
|
||||
rtx subreg, perm[16], pcv;
|
||||
rtx mem_subreg, subreg, perm[16], pcv;
|
||||
rtx tmp = gen_reg_rtx (V16QImode);
|
||||
/* 3 is leftmost element in register */
|
||||
unsigned int reorder[16] = {12,13,14,15,8,9,10,11,4,5,6,7,0,1,2,3};
|
||||
|
|
@ -1544,7 +1577,8 @@
|
|||
emit_insn (gen_altivec_vperm_v16qi_direct (tmp, operands[1],
|
||||
operands[1], pcv));
|
||||
subreg = simplify_gen_subreg (V4SImode, tmp, V16QImode, 0);
|
||||
emit_insn (gen_vsx_st_elemrev_v4si (subreg, operands[0]));
|
||||
mem_subreg = simplify_gen_subreg (V4SImode, operands[0], V16QImode, 0);
|
||||
emit_insn (gen_vsx_st_elemrev_v4si (mem_subreg, subreg));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2018-01-22 Carl Love <cel@us.ibm.com>
|
||||
* gcc.target/powerpc/powerpc.exp: Add torture tests for
|
||||
builtins-4-runnable.c, builtins-6-runnable.c,
|
||||
builtins-5-p9-runnable.c, builtins-6-p9-runnable.c.
|
||||
* gcc.target/powerpc/builtins-6-runnable.c: New test file.
|
||||
* gcc.target/powerpc/builtins-4-runnable.c: Add additional tests
|
||||
for signed/unsigned 128-bit and long long int loads.
|
||||
|
||||
2018-01-22 Marek Polacek <polacek@redhat.com>
|
||||
|
||||
PR c++/81933
|
||||
|
|
|
|||
|
|
@ -1,10 +1,13 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target vsx_hw } */
|
||||
/* { dg-options "-maltivec -mvsx" } */
|
||||
/* { dg-options "-maltivec -mvsx" } */
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <altivec.h> // vector
|
||||
|
||||
#ifdef DEBUG
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
|
||||
void abort (void);
|
||||
|
||||
|
|
@ -24,9 +27,11 @@ int main() {
|
|||
|
||||
float data_f[100];
|
||||
double data_d[100];
|
||||
|
||||
__uint128_t data_u128[100];
|
||||
__int128_t data_128[100];
|
||||
|
||||
signed long long disp;
|
||||
|
||||
|
||||
vector signed char vec_c_expected1, vec_c_expected2, vec_c_result1, vec_c_result2;
|
||||
vector unsigned char vec_uc_expected1, vec_uc_expected2,
|
||||
vec_uc_result1, vec_uc_result2;
|
||||
|
|
@ -42,11 +47,13 @@ int main() {
|
|||
vec_sll_result1, vec_sll_result2;
|
||||
vector unsigned long long vec_ull_expected1, vec_ull_expected2,
|
||||
vec_ull_result1, vec_ull_result2;
|
||||
vector __int128_t vec_128_expected1, vec_128_result1;
|
||||
vector __uint128_t vec_u128_expected1, vec_u128_result1;
|
||||
vector float vec_f_expected1, vec_f_expected2, vec_f_result1, vec_f_result2;
|
||||
vector double vec_d_expected1, vec_d_expected2, vec_d_result1, vec_d_result2;
|
||||
char buf[20];
|
||||
signed long long zero = (signed long long) 0;
|
||||
|
||||
|
||||
for (i = 0; i < 100; i++)
|
||||
{
|
||||
data_c[i] = i;
|
||||
|
|
@ -59,21 +66,304 @@ int main() {
|
|||
data_ull[i] = i+1001;
|
||||
data_f[i] = i+100000.0;
|
||||
data_d[i] = i+1000000.0;
|
||||
data_128[i] = i + 12800000;
|
||||
data_u128[i] = i + 12800001;
|
||||
}
|
||||
|
||||
disp = 0;
|
||||
|
||||
// vec_xl() tests
|
||||
disp = 1;
|
||||
|
||||
vec_c_expected1 = (vector signed char){0, 1, 2, 3, 4, 5, 6, 7,
|
||||
8, 9, 10, 11, 12, 13, 14, 15};
|
||||
vec_c_result1 = vec_xl (0, data_c);
|
||||
|
||||
vec_c_expected2 = (vector signed char){1, 2, 3, 4, 5, 6, 7, 8, 9,
|
||||
10, 11, 12, 13, 14, 15, 16};
|
||||
vec_c_result2 = vec_xl (disp, data_c);
|
||||
|
||||
vec_uc_expected1 = (vector unsigned char){1, 2, 3, 4, 5, 6, 7, 8, 9,
|
||||
10, 11, 12, 13, 14, 15, 16};
|
||||
vec_uc_result1 = vec_xl (0, data_uc);
|
||||
|
||||
vec_uc_expected2 = (vector unsigned char){2, 3, 4, 5, 6, 7, 8, 9, 10,
|
||||
11, 12, 13, 14, 15, 16, 17};
|
||||
vec_uc_result2 = vec_xl (disp, data_uc);
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
if (vec_c_result1[i] != vec_c_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_c_result1[%d] = %d; vec_c_expected1[%d] = %d\n",
|
||||
i, vec_c_result1[i], i, vec_c_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
if (vec_c_result2[i] != vec_c_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_c_result2[%d] = %d; vec_c_expected2[%d] = %d\n",
|
||||
i, vec_c_result2[i], i, vec_c_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_uc_result1[i] != vec_uc_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_uc_result1[%d] = %d; vec_uc_expected1[%d] = %d\n",
|
||||
i, vec_uc_result1[i], i, vec_uc_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_uc_result2[i] != vec_uc_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_uc_result2[%d] = %d; vec_uc_expected2[%d] = %d\n",
|
||||
i, vec_uc_result2[i], i, vec_uc_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 2;
|
||||
vec_ssi_expected1 = (vector signed short){10, 11, 12, 13, 14, 15, 16, 17};
|
||||
|
||||
vec_ssi_result1 = vec_xl (0, data_ssi);
|
||||
|
||||
vec_ssi_expected2 = (vector signed short){11, 12, 13, 14, 15, 16, 17, 18};
|
||||
vec_ssi_result2 = vec_xl (disp, data_ssi);
|
||||
|
||||
vec_usi_expected1 = (vector unsigned short){11, 12, 13, 14, 15, 16, 17, 18};
|
||||
vec_usi_result1 = vec_xl (0, data_usi);
|
||||
|
||||
vec_usi_expected2 = (vector unsigned short){12, 13, 14, 15, 16, 17, 18, 19};
|
||||
vec_usi_result2 = vec_xl (disp, data_usi);
|
||||
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
if (vec_ssi_result1[i] != vec_ssi_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ssi_result1[%d] = %d; vec_ssi_expected1[%d] = %d\n",
|
||||
i, vec_ssi_result1[i], i, vec_ssi_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
if (vec_ssi_result2[i] != vec_ssi_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ssi_result2[%d] = %d; vec_ssi_expected2[%d] = %d\n",
|
||||
i, vec_ssi_result2[i], i, vec_ssi_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_usi_result1[i] != vec_usi_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_usi_result1[%d] = %d; vec_usi_expected1[%d] = %d\n",
|
||||
i, vec_usi_result1[i], i, vec_usi_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_usi_result2[i] != vec_usi_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_usi_result2[%d] = %d; vec_usi_expected2[%d] = %d\n",
|
||||
i, vec_usi_result2[i], i, vec_usi_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 4;
|
||||
vec_si_result1 = vec_xl (zero, data_si);
|
||||
vec_si_expected1 = (vector int){100, 101, 102, 103};
|
||||
|
||||
vec_si_result2 = vec_xl (disp, data_si);
|
||||
vec_si_expected2 = (vector int){101, 102, 103, 104};
|
||||
|
||||
vec_ui_result1 = vec_xl (zero, data_ui);
|
||||
vec_ui_expected1 = (vector unsigned int){101, 102, 103, 104};
|
||||
|
||||
vec_ui_result2 = vec_xl (disp, data_ui);
|
||||
vec_ui_expected2 = (vector unsigned int){102, 103, 104, 105};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
if (vec_si_result1[i] != vec_si_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_si_result1[%d] = %d; vec_si_expected1[%d] = %d\n",
|
||||
i, vec_si_result1[i], i, vec_si_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
if (vec_si_result2[i] != vec_si_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_si_result2[%d] = %d; vec_si_expected2[%d] = %d\n",
|
||||
i, vec_si_result2[i], i, vec_si_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ui_result1[i] != vec_ui_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ui_result1[%d] = %d; vec_ui_expected1[%d] = %d\n",
|
||||
i, vec_ui_result1[i], i, vec_ui_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ui_result2[i] != vec_ui_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ui_result2[%d] = %d; vec_ui_expected1[%d] = %d\n",
|
||||
i, vec_si_result2[i], i, vec_ui_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 8;
|
||||
vec_sll_result1 = vec_xl (zero, data_sll);
|
||||
vec_sll_expected1 = (vector signed long long){1000, 1001};
|
||||
|
||||
vec_sll_result2 = vec_xl (disp, data_sll);
|
||||
vec_sll_expected2 = (vector signed long long){1001, 1002};
|
||||
|
||||
vec_ull_result1 = vec_xl (zero, data_ull);
|
||||
vec_ull_expected1 = (vector unsigned long long){1001, 1002};
|
||||
|
||||
vec_ull_result2 = vec_xl (disp, data_ull);
|
||||
vec_ull_expected2 = (vector unsigned long long){1002, 1003};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
if (vec_sll_result1[i] != vec_sll_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_sll_result1[%d] = %lld; vec_sll_expected1[%d] = %lld\n",
|
||||
i, vec_sll_result1[i], i, vec_sll_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_sll_result2[i] != vec_sll_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_sll_result2[%d] = %lld; vec_sll_expected2[%d] = %lld\n",
|
||||
i, vec_sll_result2[i], i, vec_sll_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ull_result1[i] != vec_ull_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ull_result1[%d] = %lld; vec_ull_expected1[%d] = %lld\n",
|
||||
i, vec_ull_result1[i], i, vec_ull_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ull_result2[i] != vec_ull_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_ull_result2[%d] = %lld; vec_ull_expected2[%d] = %lld\n",
|
||||
i, vec_ull_result2[i], i, vec_ull_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 4;
|
||||
vec_f_result1 = vec_xl (zero, data_f);
|
||||
vec_f_expected1 = (vector float){100000.0, 100001.0, 100002.0, 100003.0};
|
||||
|
||||
vec_f_result2 = vec_xl (disp, data_f);
|
||||
vec_f_expected2 = (vector float){100001.0, 100002.0, 100003.0, 100004.0};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
if (vec_f_result1[i] != vec_f_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_f_result1[%d] = %f; vec_f_expected1[%d] = %f\n",
|
||||
i, vec_f_result1[i], i, vec_f_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_f_result2[i] != vec_f_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_f_result2[%d] = %f; vec_f_expected2[%d] = %f\n",
|
||||
i, vec_f_result2[i], i, vec_f_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 8;
|
||||
vec_d_result1 = vec_xl (zero, data_d);
|
||||
vec_d_expected1 = (vector double){1000000.0, 1000001.0};
|
||||
|
||||
vec_d_result2 = vec_xl (disp, data_d);
|
||||
vec_d_expected2 = (vector double){1000001.0, 1000002.0};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
if (vec_d_result1[i] != vec_d_expected1[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_d_result1[%d] = %f; vec_f_expected1[%d] = %f\n",
|
||||
i, vec_d_result1[i], i, vec_d_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_d_result2[i] != vec_d_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_d_result2[%d] = %f; vec_f_expected2[%d] = %f\n",
|
||||
i, vec_d_result2[i], i, vec_d_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_128_expected1 = (vector __int128_t){12800000};
|
||||
vec_128_result1 = vec_xl (zero, data_128);
|
||||
|
||||
if (vec_128_expected1[0] != vec_128_result1[0])
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_128_result1[0] = %lld %llu; ",
|
||||
vec_128_result1[0] >> 64,
|
||||
vec_128_result1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF);
|
||||
printf("vec_128_expected1[0] = %lld %llu\n",
|
||||
vec_128_expected1[0] >> 64,
|
||||
vec_128_expected1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_u128_result1 = vec_xl (zero, data_u128);
|
||||
vec_u128_expected1 = (vector __uint128_t){12800001};
|
||||
if (vec_u128_expected1[0] != vec_u128_result1[0])
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl(), vec_u128_result1[0] = %lld; ",
|
||||
vec_u128_result1[0] >> 64,
|
||||
vec_u128_result1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF);
|
||||
printf("vec_u128_expected1[0] = %lld\n",
|
||||
vec_u128_expected1[0] >> 64,
|
||||
vec_u128_expected1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
// vec_xl_be() tests
|
||||
disp = 1;
|
||||
#ifdef __BIG_ENDIAN__
|
||||
printf("BIG ENDIAN\n");
|
||||
vec_c_expected1 = (vector signed char){0, 1, 2, 3, 4, 5, 6, 7,
|
||||
8, 9, 10, 11, 12, 13, 14, 15};
|
||||
#else
|
||||
printf("LITTLE ENDIAN\n");
|
||||
vec_c_expected1 = (vector signed char){15, 14, 13, 12, 11, 10, 9, 8,
|
||||
7, 6, 5, 4, 3, 2, 1, 0};
|
||||
#endif
|
||||
vec_c_result1 = vec_xl_be (0, data_c);
|
||||
|
||||
disp = 1;
|
||||
|
||||
|
||||
#ifdef __BIG_ENDIAN__
|
||||
vec_c_expected2 = (vector signed char){1, 2, 3, 4, 5, 6, 7, 8,
|
||||
|
|
@ -108,16 +398,36 @@ int main() {
|
|||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
if (vec_c_result1[i] != vec_c_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_c_result1[%d] = %d; vec_c_expected1[%d] = %d\n",
|
||||
i, vec_c_result1[i], i, vec_c_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_c_result2[i] != vec_c_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_c_result2[%d] = %d; vec_c_expected2[%d] = %d\n",
|
||||
i, vec_c_result2[i], i, vec_c_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_uc_result1[i] != vec_uc_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_uc_result1[%d] = %d; vec_uc_expected1[%d] = %d\n",
|
||||
i, vec_uc_result1[i], i, vec_uc_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_uc_result2[i] != vec_uc_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_uc_result2[%d] = %d; vec_uc_expected2[%d] = %d\n",
|
||||
i, vec_uc_result1[i], i, vec_uc_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_ssi_result1 = vec_xl_be (zero, data_ssi);
|
||||
|
|
@ -144,7 +454,7 @@ int main() {
|
|||
#else
|
||||
vec_usi_expected1 = (vector unsigned short){18, 17, 16, 15, 14, 13, 12, 11};
|
||||
#endif
|
||||
|
||||
|
||||
disp = 2;
|
||||
vec_usi_result2 = vec_xl_be (disp, data_usi);
|
||||
|
||||
|
|
@ -157,16 +467,36 @@ int main() {
|
|||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
if (vec_ssi_result1[i] != vec_ssi_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ssi_result1[%d] = %d; vec_ssi_expected1[%d] = %d\n",
|
||||
i, vec_ssi_result1[i], i, vec_ssi_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ssi_result2[i] != vec_ssi_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ssi_result2[%d] = %d; vec_ssi_expected2[%d] = %d\n",
|
||||
i, vec_ssi_result2[i], i, vec_ssi_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_usi_result1[i] != vec_usi_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_usi_result1[%d] = %d; vec_usi_expected1[%d] = %d\n",
|
||||
i, vec_usi_result1[i], i, vec_usi_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_usi_result2[i] != vec_usi_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_usi_result2[%d] = %d; vec_usi_expected2[%d] = %d\n",
|
||||
i, vec_usi_result2[i], i, vec_usi_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_si_result1 = vec_xl_be (zero, data_si);
|
||||
|
|
@ -207,16 +537,36 @@ int main() {
|
|||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
if (vec_si_result1[i] != vec_si_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_si_result1[%d] = %d; vec_si_expected1[%d] = %d\n",
|
||||
i, vec_si_result1[i], i, vec_si_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_si_result2[i] != vec_si_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_si_result2[%d] = %d; vec_si_expected2[%d] = %d\n",
|
||||
i, vec_si_result2[i], i, vec_si_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ui_result1[i] != vec_ui_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ui_result1[%d] = %d; vec_ui_expected1[%d] = %d\n",
|
||||
i, vec_ui_result1[i], i, vec_ui_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ui_result2[i] != vec_ui_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ui_result2[%d] = %d; vec_ui_expected2[%d] = %d\n",
|
||||
i, vec_ui_result2[i], i, vec_ui_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_sll_result1 = vec_xl_be (zero, data_sll);
|
||||
|
|
@ -257,16 +607,36 @@ int main() {
|
|||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
if (vec_sll_result1[i] != vec_sll_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_sll_result1[%d] = %lld; vec_sll_expected1[%d] = %d\n",
|
||||
i, vec_sll_result1[i], i, vec_sll_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_sll_result2[i] != vec_sll_expected2[i])
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_sll_result2[%d] = %lld; vec_sll_expected2[%d] = %d\n",
|
||||
i, vec_sll_result2[i], i, vec_sll_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ull_result1[i] != vec_ull_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ull_result1[%d] = %lld; vec_ull_expected1[%d] = %d\n",
|
||||
i, vec_ull_result1[i], i, vec_ull_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_ull_result2[i] != vec_ull_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_ull_result2[%d] = %lld; vec_ull_expected2[%d] = %d\n",
|
||||
i, vec_ull_result2[i], i, vec_sll_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_f_result1 = vec_xl_be (zero, data_f);
|
||||
|
|
@ -289,9 +659,20 @@ int main() {
|
|||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
if (vec_f_result1[i] != vec_f_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_f_result1[%d] = %f; vec_f_expected1[%d] = %f\n",
|
||||
i, vec_f_result1[i], i, vec_f_expected1[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_f_result2[i] != vec_f_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_f_result2[%d] = %f; vec_f_expected2[%d] = %f\n",
|
||||
i, vec_f_result2[i], i, vec_f_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
vec_d_result1 = vec_xl_be (zero, data_d);
|
||||
|
|
@ -314,8 +695,63 @@ int main() {
|
|||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
if (vec_d_result1[i] != vec_d_expected1[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_d_result2[%d] = %f; vec_d_expected2[%d] = %f\n",
|
||||
i, vec_d_result2[i], i, vec_d_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (vec_d_result2[i] != vec_d_expected2[i])
|
||||
abort ();
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_d_result2[%d] = %f; vec_d_expected2[%d] = %f\n",
|
||||
i, vec_d_result2[i], i, vec_d_expected2[i]);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
disp = 0;
|
||||
vec_128_result1 = vec_xl_be (zero, data_128);
|
||||
#ifdef __BIG_ENDIAN__
|
||||
vec_128_expected1 = (vector __int128_t){ (__int128_t)12800000 };
|
||||
#else
|
||||
vec_128_expected1 = (vector __int128_t){ (__int128_t)12800000 };
|
||||
#endif
|
||||
|
||||
if (vec_128_expected1[0] != vec_128_result1[0])
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_128_result1[0] = %llu %llu;",
|
||||
vec_128_result1[0] >> 64,
|
||||
vec_128_result1[0] & 0xFFFFFFFFFFFFFFFF);
|
||||
printf(" vec_128_expected1[0] = %llu %llu\n",
|
||||
vec_128_expected1[0] >> 64,
|
||||
vec_128_expected1[0] & 0xFFFFFFFFFFFFFFFF);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __BIG_ENDIAN__
|
||||
vec_u128_expected1 = (vector __uint128_t){ (__uint128_t)12800001 };
|
||||
#else
|
||||
vec_u128_expected1 = (vector __uint128_t){ (__uint128_t)12800001 };
|
||||
#endif
|
||||
|
||||
vec_u128_result1 = vec_xl_be (zero, data_u128);
|
||||
|
||||
if (vec_u128_expected1[0] != vec_u128_result1[0])
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf("Error: vec_xl_be(), vec_u128_result1[0] = %llu %llu;",
|
||||
vec_u128_result1[0] >> 64,
|
||||
vec_u128_result1[0] & 0xFFFFFFFFFFFFFFFF);
|
||||
printf(" vec_u128_expected1[0] = %llu %llu\n",
|
||||
vec_u128_expected1[0] >> 64,
|
||||
vec_u128_expected1[0] & 0xFFFFFFFFFFFFFFFF);
|
||||
#else
|
||||
abort ();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
1001
gcc/testsuite/gcc.target/powerpc/builtins-6-runnable.c
Normal file
1001
gcc/testsuite/gcc.target/powerpc/builtins-6-runnable.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -49,4 +49,16 @@ gcc-dg-runtest [list $srcdir/$subdir/savres.c] "" $alti
|
|||
|
||||
# All done.
|
||||
torture-finish
|
||||
|
||||
torture-init
|
||||
# Test load/store builtins at multiple optimizations
|
||||
set-torture-options [list -O0 -Os -O1 -O2 -O3]
|
||||
gcc-dg-runtest [list $srcdir/$subdir/builtins-4-runnable.c \
|
||||
$srcdir/$subdir/builtins-6-runnable.c \
|
||||
$srcdir/$subdir/builtins-5-p9-runnable.c \
|
||||
$srcdir/$subdir/builtins-6-p9-runnable.c] "" $DEFAULT_CFLAGS
|
||||
|
||||
# All done.
|
||||
torture-finish
|
||||
|
||||
dg-finish
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue