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sparc.c (sparc_expand_vec_perm_bmask): Use a scratch register as destination of bmask.

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* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use a scratch
	register as destination of bmask.
	(vector_init_bshuffle): Likewise.
	* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
	(bmaskdi_vis): Enable only in 64-bit mode.

From-SVN: r241205
This commit is contained in:
Eric Botcazou 2016-10-15 22:40:12 +00:00 • committed by Eric Botcazou
parent 68d0192058
commit d0d48a06df
6 changed files with 60 additions and 4 deletions
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8
gcc/ChangeLog
View file

@ -1,3 +1,11 @@
2016-10-15 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use a scratch
register as destination of bmask.
(vector_init_bshuffle): Likewise.
* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
(bmaskdi_vis): Enable only in 64-bit mode.
2016-10-15 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.c (rs6000_get_separate_components): Do not

4
gcc/config/sparc/sparc.c
View file

@ -12044,7 +12044,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel)
}
/* Always perform the final addition/merge within the bmask insn. */
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
}
/* Implement TARGET_FRAME_POINTER_REQUIRED. */
@ -12310,7 +12310,7 @@ vector_init_bshuffle (rtx target, rtx elt, machine_mode mode,
}
sel = force_reg (SImode, GEN_INT (bmask));
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
emit_insn (final_insn);
}

4
gcc/config/sparc/sparc.md
View file

@ -8548,7 +8548,7 @@
(match_operand:DI 2 "register_or_zero_operand" "rJ")))
(set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_VIS2"
"TARGET_VIS2 && TARGET_ARCH64"
"bmask\t%r1, %r2, %0"
[(set_attr "type" "array")
(set_attr "v3pipe" "true")])
@ -8593,7 +8593,7 @@
mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
sel = force_reg (SImode, gen_int_mode (mask, SImode));
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
DONE;
})

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2016-10-15 Eric Botcazou <ebotcazou@adacore.com>
* gcc.target/sparc/bmaskbshuf.c: Rename to...
* gcc.target/sparc/bmaskbshuf-1.c: ...this.
* gcc.target/sparc/bmaskbshuf-2.c: New test.
2016-10-15 Eric Botcazou <ebotcazou@adacore.com>
* gcc.target/sparc/popc.c: Rename to...

0
gcc/testsuite/gcc.target/sparc/bmaskbshuf.c → gcc/testsuite/gcc.target/sparc/bmaskbshuf-1.c
View file

42
gcc/testsuite/gcc.target/sparc/bmaskbshuf-2.c Normal file
View file

@ -0,0 +1,42 @@
/* { dg-do run } */
/* { dg-require-effective-target ultrasparc_vis2_hw } */
/* { dg-options "-mcpu=ultrasparc3 -O" } */
typedef unsigned int Vect __attribute__((vector_size(8)));
extern void abort (void);
Vect a, b, c, d;
__attribute__((noinline, noclone)) void test (void)
{
Vect mask = { 2, 2 };
int i;
c = __builtin_shuffle (a, mask);
d = __builtin_shuffle (a, b, mask);
__asm__ ("" : : "r" (&c), "r" (&d) : "memory");
for (i = 0; i < 2; ++i)
if (c[i] != a[mask[i] & 1])
abort ();
else if (mask[i] & 2)
{
if (d[i] != b[mask[i] & 1])
abort ();
}
}
int main (void)
{
int i;
for (i = 0; i < 2; ++i)
{
a[i] = i + 2;
b[i] = 2 + i + 2;
}
test ();
return 0;
}