S/390: Use signaling FP comparison instructions
dg-torture.exp=inf-compare-1.c is failing, because (qNaN > +Inf) comparison is compiled to CDB instruction, which does not signal an invalid operation exception. KDB should have been used instead. This patch introduces a new CCmode and a new pattern in order to generate signaling instructions in this and similar cases. gcc/ChangeLog: 2019-10-11 Ilya Leoshkevich <iii@linux.ibm.com> PR target/77918 * config/s390/2827.md: Add new opcodes. * config/s390/2964.md: Likewise. * config/s390/3906.md: Likewise. * config/s390/8561.md: Likewise. * config/s390/s390-builtins.def (s390_vfchesb): Use the new vec_cmpgev4sf_quiet_nocc. (s390_vfchedb): Use the new vec_cmpgev2df_quiet_nocc. (s390_vfchsb): Use the new vec_cmpgtv4sf_quiet_nocc. (s390_vfchdb): Use the new vec_cmpgtv2df_quiet_nocc. (vec_cmplev4sf): Use the new vec_cmplev4sf_quiet_nocc. (vec_cmplev2df): Use the new vec_cmplev2df_quiet_nocc. (vec_cmpltv4sf): Use the new vec_cmpltv4sf_quiet_nocc. (vec_cmpltv2df): Use the new vec_cmpltv2df_quiet_nocc. * config/s390/s390-modes.def (CCSFPS): New mode. * config/s390/s390.c (s390_match_ccmode_set): Support CCSFPS. (s390_select_ccmode): Return CCSFPS for LT, LE, GT, GE and LTGT. (s390_branch_condition_mask): Reuse CCS for CCSFPS. (s390_expand_vec_compare): Use non-signaling patterns where necessary. (s390_reverse_condition): Support CCSFPS. * config/s390/s390.md (*cmp<mode>_ccsfps): New pattern. * config/s390/vector.md: (VFCMP_HW_OP): Remove. (asm_fcmp_op): Likewise. (*smaxv2df3_vx): Use pattern for quiet comparison. (*sminv2df3_vx): Likewise. (*vec_cmp<VFCMP_HW_OP:code><mode>_nocc): Remove. (*vec_cmpeq<mode>_quiet_nocc): New pattern. (vec_cmpgt<mode>_quiet_nocc): Likewise. (vec_cmplt<mode>_quiet_nocc): New expander. (vec_cmpge<mode>_quiet_nocc): New pattern. (vec_cmple<mode>_quiet_nocc): New expander. (*vec_cmpeq<mode>_signaling_nocc): New pattern. (*vec_cmpgt<mode>_signaling_nocc): Likewise. (*vec_cmpgt<mode>_signaling_finite_nocc): Likewise. (*vec_cmpge<mode>_signaling_nocc): Likewise. (*vec_cmpge<mode>_signaling_finite_nocc): Likewise. (vec_cmpungt<mode>): New expander. (vec_cmpunge<mode>): Likewise. (vec_cmpuneq<mode>): Use quiet patterns. (vec_cmpltgt<mode>): Allow only on z14+. (vec_cmpordered<mode>): Use quiet patterns. (vec_cmpunordered<mode>): Likewise. (VEC_CMP_EXPAND): Add ungt and unge. gcc/testsuite/ChangeLog: 2019-10-11 Ilya Leoshkevich <iii@linux.ibm.com> * gcc.target/s390/vector/vec-scalar-cmp-1.c: Adjust expectations. From-SVN: r276871
This commit is contained in:
Ilya Leoshkevich
Ilya Leoshkevich
parent
1fcf52a6a2
commit
d0a0cacaba
12 changed files with 292 additions and 74 deletions
|
|
@ -1,3 +1,50 @@
|
|||
2019-10-11 Ilya Leoshkevich <iii@linux.ibm.com>
|
||||
|
||||
PR target/77918
|
||||
* config/s390/2827.md: Add new opcodes.
|
||||
* config/s390/2964.md: Likewise.
|
||||
* config/s390/3906.md: Likewise.
|
||||
* config/s390/8561.md: Likewise.
|
||||
* config/s390/s390-builtins.def (s390_vfchesb): Use
|
||||
the new vec_cmpgev4sf_quiet_nocc.
|
||||
(s390_vfchedb): Use the new vec_cmpgev2df_quiet_nocc.
|
||||
(s390_vfchsb): Use the new vec_cmpgtv4sf_quiet_nocc.
|
||||
(s390_vfchdb): Use the new vec_cmpgtv2df_quiet_nocc.
|
||||
(vec_cmplev4sf): Use the new vec_cmplev4sf_quiet_nocc.
|
||||
(vec_cmplev2df): Use the new vec_cmplev2df_quiet_nocc.
|
||||
(vec_cmpltv4sf): Use the new vec_cmpltv4sf_quiet_nocc.
|
||||
(vec_cmpltv2df): Use the new vec_cmpltv2df_quiet_nocc.
|
||||
* config/s390/s390-modes.def (CCSFPS): New mode.
|
||||
* config/s390/s390.c (s390_match_ccmode_set): Support CCSFPS.
|
||||
(s390_select_ccmode): Return CCSFPS for LT, LE, GT, GE and LTGT.
|
||||
(s390_branch_condition_mask): Reuse CCS for CCSFPS.
|
||||
(s390_expand_vec_compare): Use non-signaling patterns where
|
||||
necessary.
|
||||
(s390_reverse_condition): Support CCSFPS.
|
||||
* config/s390/s390.md (*cmp<mode>_ccsfps): New pattern.
|
||||
* config/s390/vector.md: (VFCMP_HW_OP): Remove.
|
||||
(asm_fcmp_op): Likewise.
|
||||
(*smaxv2df3_vx): Use pattern for quiet comparison.
|
||||
(*sminv2df3_vx): Likewise.
|
||||
(*vec_cmp<VFCMP_HW_OP:code><mode>_nocc): Remove.
|
||||
(*vec_cmpeq<mode>_quiet_nocc): New pattern.
|
||||
(vec_cmpgt<mode>_quiet_nocc): Likewise.
|
||||
(vec_cmplt<mode>_quiet_nocc): New expander.
|
||||
(vec_cmpge<mode>_quiet_nocc): New pattern.
|
||||
(vec_cmple<mode>_quiet_nocc): New expander.
|
||||
(*vec_cmpeq<mode>_signaling_nocc): New pattern.
|
||||
(*vec_cmpgt<mode>_signaling_nocc): Likewise.
|
||||
(*vec_cmpgt<mode>_signaling_finite_nocc): Likewise.
|
||||
(*vec_cmpge<mode>_signaling_nocc): Likewise.
|
||||
(*vec_cmpge<mode>_signaling_finite_nocc): Likewise.
|
||||
(vec_cmpungt<mode>): New expander.
|
||||
(vec_cmpunge<mode>): Likewise.
|
||||
(vec_cmpuneq<mode>): Use quiet patterns.
|
||||
(vec_cmpltgt<mode>): Allow only on z14+.
|
||||
(vec_cmpordered<mode>): Use quiet patterns.
|
||||
(vec_cmpunordered<mode>): Likewise.
|
||||
(VEC_CMP_EXPAND): Add ungt and unge.
|
||||
|
||||
2019-10-11 Jan Hubicka <hubicka@ucw.cz>
|
||||
|
||||
* gimple-streamer-out.c (output_gimple_stmt): Add explicit function
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
|
||||
(define_insn_reservation "zEC12_normal_fp" 8
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing")
|
||||
(eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb,keb,kebr,kdb,kdbr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_cgdbr" 2
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
|
|
@ -426,6 +426,10 @@
|
|||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "cxbr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_kxbr" 18
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "kxbr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_ddbr" 36
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "ddbr")) "nothing")
|
||||
|
|
@ -578,10 +582,18 @@
|
|||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "cdtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_kdtr" 11
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "kdtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_cxtr" 14
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "cxtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_kxtr" 14
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "kxtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "zEC12_slbg" 3
|
||||
(and (eq_attr "cpu" "zEC12")
|
||||
(eq_attr "mnemonic" "slbg")) "nothing")
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ ng,ni,niy,ntstg,ny,o,og,oi,oiy,oy,s,sar,sdb,seb,sfpc,sg,sgf,sh,shy,sl,\
|
|||
slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,stey,stg,stgrl,\
|
||||
sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,tabort,tm,tmy,vl,\
|
||||
vlbb,vleb,vlef,vleg,vleh,vll,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,\
|
||||
vlrepf,vlrepg,vlreph,vst,vstl,x,xg,xi,xiy,xy")
|
||||
vlrepf,vlrepg,vlreph,vst,vstl,x,xg,xi,xiy,xy,kdb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z13_unit_vfu" ""
|
||||
|
|
@ -109,7 +109,8 @@ vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,wcdgb,wcdlgb,wcgdb,wclgdb,wfadb,\
|
|||
wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexbs,wfchdb,wfchedb,wfchesb,wfchexb,\
|
||||
wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfisb,wfixb,wflcdb,wflcsb,wflcxb,wflld,\
|
||||
wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmadb,wfmasb,wfmaxb,wfmdb,wfmsb,\
|
||||
wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb")
|
||||
wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb,kebr,kdb,kdbr,kxbr,\
|
||||
kdtr,kxtr,wfkdb,wfksb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z13_cracked" ""
|
||||
|
|
@ -131,7 +132,7 @@ stmg,stmy,tbegin,tbeginc")
|
|||
cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\
|
||||
lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,ml,mlg,\
|
||||
mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,sfpc,slb,slbg,slbgr,slbr,\
|
||||
sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc")
|
||||
sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z13_endgroup" ""
|
||||
|
|
@ -198,7 +199,7 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\
|
|||
vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\
|
||||
vistrh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlvgp,\
|
||||
vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,vslb,vsrab,vsrlb,wfcdb,wfcexbs,\
|
||||
wfchexbs,wfchxbs,wfcsb")) "nothing")
|
||||
wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing")
|
||||
|
||||
(define_insn_reservation "z13_3" 3
|
||||
(and (eq_attr "cpu" "z13")
|
||||
|
|
@ -232,7 +233,7 @@ wfmdb,wfmsb,wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb")) "nothing
|
|||
(and (eq_attr "cpu" "z13")
|
||||
(eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,msg,msgr,sdtr,tdcdt,tdcet,\
|
||||
vcdgb,vcdlgb,vcgdb,vclgdb,vfadb,vfasb,vfidb,vfisb,vfmadb,vfmasb,vfmdb,vfmsb,\
|
||||
vfmsdb,vfmssb,vfsdb,vfssb,vldeb,vledb")) "nothing")
|
||||
vfmsdb,vfmssb,vfsdb,vfssb,vldeb,vledb,kdtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "z13_8" 8
|
||||
(and (eq_attr "cpu" "z13")
|
||||
|
|
@ -254,7 +255,7 @@ celgbr,flogr,m,madb,maeb,maebr,mfy,ml,mlr,mr,msdb,mseb,msebr")) "nothing")
|
|||
(define_insn_reservation "z13_12" 12
|
||||
(and (eq_attr "cpu" "z13")
|
||||
(eq_attr "mnemonic" "cfdbr,cfebr,cgdbr,cgebr,clfdbr,clfebr,clgdbr,\
|
||||
clgebr,cxbr,cxtr,mlg,mlgr,tcxb,tdcxt")) "nothing")
|
||||
clgebr,cxbr,cxtr,mlg,mlgr,tcxb,tdcxt,kxbr,kxtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "z13_13" 13
|
||||
(and (eq_attr "cpu" "z13")
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,\
|
|||
stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,\
|
||||
tabort,tm,tmy,vl,vlbb,vleb,vlef,vleg,vleh,vll,vllezb,vllezf,vllezg,vllezh,\
|
||||
vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr,vst,vstl,vstrl,vstrlr,x,xg,xi,\
|
||||
xiy,xy")
|
||||
xiy,xy,kdb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z14_unit_vfu" ""
|
||||
|
|
@ -113,7 +113,8 @@ wfadb,wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexbs,wfchdb,wfchedb,wfchesb,\
|
|||
wfchexb,wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfisb,wfixb,wflcdb,wflcsb,wflcxb,\
|
||||
wflld,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmadb,wfmasb,wfmaxb,\
|
||||
wfmaxxb,wfmdb,wfminxb,wfmsb,wfmsdb,wfmssb,wfmsxb,wfmxb,wfnmaxb,wfnmsxb,wfsdb,\
|
||||
wfssb,wfsxb,wldeb,wledb")
|
||||
wfssb,wfsxb,wldeb,wledb,kebr,kdb,kdbr,kxbr,kdtr,kxtr,wfkdb,wfksb,vfkesb,\
|
||||
vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z14_cracked" ""
|
||||
|
|
@ -135,7 +136,7 @@ stmg,stmy,tbegin,tbeginc")
|
|||
cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\
|
||||
lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\
|
||||
ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,ppa,sfpc,slb,slbg,\
|
||||
slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc")
|
||||
slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z14_endgroup" ""
|
||||
|
|
@ -192,7 +193,8 @@ vrepig,vrepih,vsb,vsbiq,vscbib,vscbif,vscbig,vscbih,vscbiq,vsegb,vsegf,vsegh,\
|
|||
vsel,vsf,vsg,vsh,vsl,vslb,vsldb,vsq,vsra,vsrab,vsrl,vsrlb,vuphb,vuphf,\
|
||||
vuphh,vuplb,vuplf,vuplhb,vuplhf,vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,\
|
||||
wfcedb,wfcesb,wfchdb,wfchedb,wfchesb,wfchexb,wfchsb,wfchxb,wflcdb,wflcsb,\
|
||||
wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,xiy")) "nothing")
|
||||
wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,xiy,\
|
||||
vfkesb,vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")) "nothing")
|
||||
|
||||
(define_insn_reservation "z14_2" 2
|
||||
(and (eq_attr "cpu" "z14")
|
||||
|
|
@ -204,7 +206,7 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\
|
|||
vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\
|
||||
vistrh,vlgvf,vlgvg,vlgvh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,\
|
||||
vlrepg,vlreph,vlrl,vlvgp,vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,wfcdb,\
|
||||
wfcexbs,wfchexbs,wfchxbs,wfcsb")) "nothing")
|
||||
wfcexbs,wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing")
|
||||
|
||||
(define_insn_reservation "z14_3" 3
|
||||
(and (eq_attr "cpu" "z14")
|
||||
|
|
@ -238,7 +240,8 @@ wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing")
|
|||
(define_insn_reservation "z14_7" 7
|
||||
(and (eq_attr "cpu" "z14")
|
||||
(eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,msgrkc,sdtr,tdcdt,tdcet,\
|
||||
vfasb,vfisb,vfmasb,vfmsb,vfmssb,vfnmssb,vfssb,vgef,vgeg,wflld")) "nothing")
|
||||
vfasb,vfisb,vfmasb,vfmsb,vfmssb,vfnmssb,vfssb,vgef,vgeg,wflld,kdtr"))
|
||||
"nothing")
|
||||
|
||||
(define_insn_reservation "z14_8" 8
|
||||
(and (eq_attr "cpu" "z14")
|
||||
|
|
@ -261,7 +264,7 @@ celgbr,madb,maeb,maebr,msdb,mseb,msebr,vscef,vsceg")) "nothing")
|
|||
(define_insn_reservation "z14_12" 12
|
||||
(and (eq_attr "cpu" "z14")
|
||||
(eq_attr "mnemonic" "cfdbr,cfebr,cgdbr,cgebr,clfdbr,clfebr,clgdbr,\
|
||||
clgebr,cxbr,cxtr,tcxb,tdcxt")) "nothing")
|
||||
clgebr,cxbr,cxtr,tcxb,tdcxt,kxbr,kxtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "z14_13" 13
|
||||
(and (eq_attr "cpu" "z14")
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ sar,sdb,seb,sfpc,sg,sgf,sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,\
|
|||
stc,stcy,std,stdy,ste,stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,\
|
||||
strvg,strvh,sty,sy,tabort,tm,tmy,vl,vlbb,vleb,vlef,vleg,vleh,vll,vllezb,\
|
||||
vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr,vst,\
|
||||
vstef,vsteg,vstl,vstrl,vstrlr,x,xg,xi,xiy,xy")
|
||||
vstef,vsteg,vstl,vstrl,vstrlr,x,xg,xi,xiy,xy,keb,kdb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z15_unit_vfu" ""
|
||||
|
|
@ -112,7 +112,9 @@ vupllf,vupllh,vx,vzero,wfadb,wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexb,wfcexbs,\
|
|||
wfchdb,wfchedb,wfchesb,wfchexb,wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfidb,\
|
||||
wfisb,wfixb,wflcdb,wflcsb,wflcxb,wflld,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,\
|
||||
wflpxb,wfmadb,wfmasb,wfmaxb,wfmaxxb,wfmdb,wfminxb,wfmsb,wfmsdb,wfmssb,wfmsxb,\
|
||||
wfmxb,wfnmaxb,wfnmsxb,wfsdb,wfssb,wfsxb,wldeb,wledb")
|
||||
wfmxb,wfnmaxb,wfnmsxb,wfsdb,wfssb,wfsxb,wldeb,wledb,keb,kebr,kdb,kdbr,kxbr,\
|
||||
kdtr,kxtr,wfkdb,wfksb,vfkesb,vfkedb,wfkexb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,\
|
||||
vfkhedb,wfkhexb")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z15_cracked" ""
|
||||
|
|
@ -134,7 +136,7 @@ stam,stm,stmg,stmy,tbegin,tbeginc")
|
|||
cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\
|
||||
lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\
|
||||
ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,nc,oc,ppa,sfpc,slb,slbg,\
|
||||
slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc")
|
||||
slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr")
|
||||
(const_int 1)] (const_int 0)))
|
||||
|
||||
(define_attr "z15_endgroup" ""
|
||||
|
|
@ -194,7 +196,8 @@ vsel,vsf,vsg,vsh,vsl,vslb,vsldb,vsq,vsra,vsrab,vsrl,vsrlb,vuphb,vuphf,\
|
|||
vuphh,vuplb,vuplf,vuplhb,vuplhf,vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,\
|
||||
wfcedb,wfcesb,wfcexb,wfchdb,wfchedb,wfchesb,wfchexb,wfchsb,wfchxb,wflcdb,\
|
||||
wflcsb,wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,\
|
||||
xiy")) "nothing")
|
||||
xiy,vfkesb,vfkedb,wfkexb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb"))
|
||||
"nothing")
|
||||
|
||||
(define_insn_reservation "z15_2" 2
|
||||
(and (eq_attr "cpu" "z15")
|
||||
|
|
@ -206,7 +209,8 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\
|
|||
vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\
|
||||
vistrh,vlgvb,vlgvf,vlgvg,vlgvh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,\
|
||||
vlrepf,vlrepg,vlreph,vlrl,vlvgp,vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,\
|
||||
wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb")) "nothing")
|
||||
wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb,keb,kebr,kdb,kdbr,wfkdb,wfksb"))
|
||||
"nothing")
|
||||
|
||||
(define_insn_reservation "z15_3" 3
|
||||
(and (eq_attr "cpu" "z15")
|
||||
|
|
@ -240,7 +244,7 @@ wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing")
|
|||
(define_insn_reservation "z15_7" 7
|
||||
(and (eq_attr "cpu" "z15")
|
||||
(eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,ltdtr,msgrkc,sdtr,tdcdt,\
|
||||
tdcet,vgef,vgeg")) "nothing")
|
||||
tdcet,vgef,vgeg,kdtr")) "nothing")
|
||||
|
||||
(define_insn_reservation "z15_8" 8
|
||||
(and (eq_attr "cpu" "z15")
|
||||
|
|
@ -263,7 +267,8 @@ clgebr,mg,mgrk,mlg,mlgr")) "nothing")
|
|||
|
||||
(define_insn_reservation "z15_12" 12
|
||||
(and (eq_attr "cpu" "z15")
|
||||
(eq_attr "mnemonic" "cxbr,cxftr,cxlftr,cxtr,tcxb,tdcxt")) "nothing")
|
||||
(eq_attr "mnemonic" "cxbr,cxftr,cxlftr,cxtr,tcxb,tdcxt,kxbr,kxtr"))
|
||||
"nothing")
|
||||
|
||||
(define_insn_reservation "z15_13" 13
|
||||
(and (eq_attr "cpu" "z15")
|
||||
|
|
|
|||
|
|
@ -1495,8 +1495,8 @@ B_DEF (vec_cmpgev4si, vec_cmpgev4si, 0,
|
|||
B_DEF (vec_cmpgeuv4si, vec_cmpgeuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
|
||||
B_DEF (vec_cmpgev2di, vec_cmpgev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (vec_cmpgeuv2di, vec_cmpgeuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (s390_vfchesb, vec_cmpgev4sf, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (s390_vfchedb, vec_cmpgev2df, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
B_DEF (s390_vfchesb, vec_cmpgev4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (s390_vfchedb, vec_cmpgev2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
|
||||
OB_DEF (s390_vec_cmpgt, s390_vec_cmpgt_s8, s390_vec_cmpgt_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
|
||||
OB_DEF_VAR (s390_vec_cmpgt_s8, s390_vchb, 0, 0, BT_OV_BV16QI_V16QI_V16QI)
|
||||
|
|
@ -1518,8 +1518,8 @@ B_DEF (s390_vchf, vec_cmpgtv4si, 0,
|
|||
B_DEF (s390_vchlf, vec_cmpgtuv4si, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
|
||||
B_DEF (s390_vchg, vec_cmpgtv2di, 0, B_VX, 0, BT_FN_V2DI_V2DI_V2DI)
|
||||
B_DEF (s390_vchlg, vec_cmpgtuv2di, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (s390_vfchsb, vec_cmpgtv4sf, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (s390_vfchdb, vec_cmpgtv2df, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
B_DEF (s390_vfchsb, vec_cmpgtv4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (s390_vfchdb, vec_cmpgtv2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
|
||||
OB_DEF (s390_vec_cmple, s390_vec_cmple_s8, s390_vec_cmple_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
|
||||
OB_DEF_VAR (s390_vec_cmple_s8, vec_cmplev16qi, 0, 0, BT_OV_BV16QI_V16QI_V16QI)
|
||||
|
|
@ -1541,8 +1541,8 @@ B_DEF (vec_cmplev4si, vec_cmplev4si, 0,
|
|||
B_DEF (vec_cmpleuv4si, vec_cmpleuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
|
||||
B_DEF (vec_cmplev2di, vec_cmplev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (vec_cmpleuv2di, vec_cmpleuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (vec_cmplev4sf, vec_cmplev4sf, 0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (vec_cmplev2df, vec_cmplev2df, 0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
B_DEF (vec_cmplev4sf, vec_cmplev4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (vec_cmplev2df, vec_cmplev2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
|
||||
OB_DEF (s390_vec_cmplt, s390_vec_cmplt_s8, s390_vec_cmplt_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
|
||||
OB_DEF_VAR (s390_vec_cmplt_s8, vec_cmpltv16qi, 0, 0, BT_OV_BV16QI_V16QI_V16QI)
|
||||
|
|
@ -1564,8 +1564,8 @@ B_DEF (vec_cmpltv4si, vec_cmpltv4si, 0,
|
|||
B_DEF (vec_cmpltuv4si, vec_cmpltuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI)
|
||||
B_DEF (vec_cmpltv2di, vec_cmpltv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (vec_cmpltuv2di, vec_cmpltuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI)
|
||||
B_DEF (vec_cmpltv4sf, vec_cmpltv4sf, 0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (vec_cmpltv2df, vec_cmpltv2df, 0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
B_DEF (vec_cmpltv4sf, vec_cmpltv4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF)
|
||||
B_DEF (vec_cmpltv2df, vec_cmpltv2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF)
|
||||
|
||||
OB_DEF (s390_vec_cntlz, s390_vec_cntlz_s8, s390_vec_cntlz_u64, B_VX, BT_FN_OV4SI_OV4SI)
|
||||
OB_DEF_VAR (s390_vec_cntlz_s8, s390_vclzb, 0, 0, BT_OV_UV16QI_V16QI)
|
||||
|
|
|
|||
|
|
@ -52,6 +52,8 @@ CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y,
|
|||
ADB/R, AEB/R, SDB/R, SEB/R,
|
||||
SRAG, SRA, SRDA)
|
||||
CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
|
||||
CCSFPS: EQ LT GT UNORDERED (KEB/R, KDB/R, KXBR, KDTR,
|
||||
KXTR, WFK)
|
||||
|
||||
Condition codes resulting from add with overflow
|
||||
|
||||
|
|
@ -140,6 +142,11 @@ around. The following both modes can be considered as CCS and CCU modes with
|
|||
exchanged operands.
|
||||
|
||||
|
||||
CCSFPS
|
||||
|
||||
This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT.
|
||||
|
||||
|
||||
CCL1, CCL2
|
||||
|
||||
These modes represent the result of overflow checks.
|
||||
|
|
@ -226,6 +233,7 @@ CC_MODE (CCU);
|
|||
CC_MODE (CCUR);
|
||||
CC_MODE (CCS);
|
||||
CC_MODE (CCSR);
|
||||
CC_MODE (CCSFPS);
|
||||
CC_MODE (CCT);
|
||||
CC_MODE (CCT1);
|
||||
CC_MODE (CCT2);
|
||||
|
|
|
|||
|
|
@ -1382,6 +1382,7 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode)
|
|||
case E_CCZ1mode:
|
||||
case E_CCSmode:
|
||||
case E_CCSRmode:
|
||||
case E_CCSFPSmode:
|
||||
case E_CCUmode:
|
||||
case E_CCURmode:
|
||||
case E_CCOmode:
|
||||
|
|
@ -1565,6 +1566,12 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
|
|||
else
|
||||
return CCAPmode;
|
||||
}
|
||||
|
||||
/* Fall through. */
|
||||
case LTGT:
|
||||
if (HONOR_NANS (op0) || HONOR_NANS (op1))
|
||||
return CCSFPSmode;
|
||||
|
||||
/* Fall through. */
|
||||
case UNORDERED:
|
||||
case ORDERED:
|
||||
|
|
@ -1573,7 +1580,6 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
|
|||
case UNLT:
|
||||
case UNGE:
|
||||
case UNGT:
|
||||
case LTGT:
|
||||
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
|
||||
&& GET_CODE (op1) != CONST_INT)
|
||||
return CCSRmode;
|
||||
|
|
@ -2088,6 +2094,7 @@ s390_branch_condition_mask (rtx code)
|
|||
break;
|
||||
|
||||
case E_CCSmode:
|
||||
case E_CCSFPSmode:
|
||||
switch (GET_CODE (code))
|
||||
{
|
||||
case EQ: return CC0;
|
||||
|
|
@ -6510,18 +6517,23 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond,
|
|||
{
|
||||
/* NE a != b -> !(a == b) */
|
||||
case NE: cond = EQ; neg_p = true; break;
|
||||
/* UNGT a u> b -> !(b >= a) */
|
||||
case UNGT: cond = GE; neg_p = true; swap_p = true; break;
|
||||
/* UNGE a u>= b -> !(b > a) */
|
||||
case UNGE: cond = GT; neg_p = true; swap_p = true; break;
|
||||
/* LE: a <= b -> b >= a */
|
||||
case UNGT:
|
||||
emit_insn (gen_vec_cmpungt (target, cmp_op1, cmp_op2));
|
||||
return;
|
||||
case UNGE:
|
||||
emit_insn (gen_vec_cmpunge (target, cmp_op1, cmp_op2));
|
||||
return;
|
||||
case LE: cond = GE; swap_p = true; break;
|
||||
/* UNLE: a u<= b -> !(a > b) */
|
||||
case UNLE: cond = GT; neg_p = true; break;
|
||||
/* UNLE: (a u<= b) -> (b u>= a). */
|
||||
case UNLE:
|
||||
emit_insn (gen_vec_cmpunge (target, cmp_op2, cmp_op1));
|
||||
return;
|
||||
/* LT: a < b -> b > a */
|
||||
case LT: cond = GT; swap_p = true; break;
|
||||
/* UNLT: a u< b -> !(a >= b) */
|
||||
case UNLT: cond = GE; neg_p = true; break;
|
||||
/* UNLT: (a u< b) -> (b u> a). */
|
||||
case UNLT:
|
||||
emit_insn (gen_vec_cmpungt (target, cmp_op2, cmp_op1));
|
||||
return;
|
||||
case UNEQ:
|
||||
emit_insn (gen_vec_cmpuneq (target, cmp_op1, cmp_op2));
|
||||
return;
|
||||
|
|
@ -6684,7 +6696,7 @@ s390_reverse_condition (machine_mode mode, enum rtx_code code)
|
|||
{
|
||||
/* Reversal of FP compares takes care -- an ordered compare
|
||||
becomes an unordered compare and vice versa. */
|
||||
if (mode == CCVFALLmode || mode == CCVFANYmode)
|
||||
if (mode == CCVFALLmode || mode == CCVFANYmode || mode == CCSFPSmode)
|
||||
return reverse_condition_maybe_unordered (code);
|
||||
else if (mode == CCVIALLmode || mode == CCVIANYmode)
|
||||
return reverse_condition (code);
|
||||
|
|
|
|||
|
|
@ -1423,6 +1423,20 @@
|
|||
(set_attr "cpu_facility" "*,*,vx,vxe")
|
||||
(set_attr "enabled" "*,<DSF>,<DF>,<SF>")])
|
||||
|
||||
(define_insn "*cmp<mode>_ccsfps"
|
||||
[(set (reg CC_REGNUM)
|
||||
(compare (match_operand:FP 0 "register_operand" "f,f,v,v")
|
||||
(match_operand:FP 1 "general_operand" "f,R,v,v")))]
|
||||
"s390_match_ccmode (insn, CCSFPSmode) && TARGET_HARD_FLOAT"
|
||||
"@
|
||||
k<xde><bt>r\t%0,%1
|
||||
k<xde>b\t%0,%1
|
||||
wfkdb\t%0,%1
|
||||
wfksb\t%0,%1"
|
||||
[(set_attr "op_type" "RRE,RXE,VRR,VRR")
|
||||
(set_attr "cpu_facility" "*,*,vx,vxe")
|
||||
(set_attr "enabled" "*,<DSF>,<DF>,<SF>")])
|
||||
|
||||
; Compare and Branch instructions
|
||||
|
||||
; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
|
||||
|
|
|
|||
|
|
@ -168,10 +168,6 @@
|
|||
(define_mode_attr vec_halfnumelts
|
||||
[(V4SF "V2SF") (V4SI "V2SI")])
|
||||
|
||||
; The comparisons not setting CC iterate over the rtx code.
|
||||
(define_code_iterator VFCMP_HW_OP [eq gt ge])
|
||||
(define_code_attr asm_fcmp_op [(eq "e") (gt "h") (ge "he")])
|
||||
|
||||
|
||||
|
||||
; Comparison operators on int and fp compares which are directly
|
||||
|
|
@ -1377,7 +1373,8 @@
|
|||
"#"
|
||||
"&& 1"
|
||||
[(set (match_dup 3)
|
||||
(gt:V2DI (match_dup 1) (match_dup 2)))
|
||||
(not:V2DI
|
||||
(unge:V2DI (match_dup 2) (match_dup 1))))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:V2DF
|
||||
(eq (match_dup 3) (match_dup 4))
|
||||
|
|
@ -1412,7 +1409,8 @@
|
|||
"#"
|
||||
"&& 1"
|
||||
[(set (match_dup 3)
|
||||
(gt:V2DI (match_dup 1) (match_dup 2)))
|
||||
(not:V2DI
|
||||
(unge:V2DI (match_dup 2) (match_dup 1))))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:V2DF
|
||||
(eq (match_dup 3) (match_dup 4))
|
||||
|
|
@ -1466,27 +1464,134 @@
|
|||
;; Floating point compares
|
||||
;;
|
||||
|
||||
; EQ, GT, GE
|
||||
; vfcesb, vfcedb, wfcexb, vfchsb, vfchdb, wfchxb, vfchesb, vfchedb, wfchexb
|
||||
(define_insn "*vec_cmp<VFCMP_HW_OP:code><mode>_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(VFCMP_HW_OP:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VX"
|
||||
"<vw>fc<VFCMP_HW_OP:asm_fcmp_op><sdx>b\t%v0,%v1,%v2"
|
||||
; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b)
|
||||
(define_insn "*vec_cmpeq<mode>_quiet_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(eq:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VX"
|
||||
"<vw>fce<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a))
|
||||
(define_insn "vec_cmpgt<mode>_quiet_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_operand:VFT 2 "register_operand" "v")
|
||||
(match_operand:VFT 1 "register_operand" "v"))))]
|
||||
"TARGET_VX"
|
||||
"<vw>fch<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_expand "vec_cmplt<mode>_quiet_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))))]
|
||||
"TARGET_VX")
|
||||
|
||||
; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b))
|
||||
(define_insn "vec_cmpge<mode>_quiet_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unlt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))))]
|
||||
"TARGET_VX"
|
||||
"<vw>fche<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_expand "vec_cmple<mode>_quiet_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unlt:<tointvec> (match_operand:VFT 2 "register_operand" "v")
|
||||
(match_operand:VFT 1 "register_operand" "v"))))]
|
||||
"TARGET_VX")
|
||||
|
||||
; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a))
|
||||
(define_insn "*vec_cmpeq<mode>_signaling_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(and:<tointvec>
|
||||
(ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))
|
||||
(ge:<tointvec> (match_dup 2)
|
||||
(match_dup 1))))]
|
||||
"TARGET_VXE"
|
||||
"<vw>fke<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b)
|
||||
(define_insn "*vec_cmpgt<mode>_signaling_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VXE"
|
||||
"<vw>fkh<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_insn "*vec_cmpgt<mode>_signaling_finite_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VX && !TARGET_VXE && flag_finite_math_only"
|
||||
"<vw>fch<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b)
|
||||
(define_insn "*vec_cmpge<mode>_signaling_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VXE"
|
||||
"<vw>fkhe<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_insn "*vec_cmpge<mode>_signaling_finite_nocc"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))]
|
||||
"TARGET_VX && !TARGET_VXE && flag_finite_math_only"
|
||||
"<vw>fche<sdx>b\t%v0,%v1,%v2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
; Expanders for not directly supported comparisons
|
||||
; Signaling comparisons must be expressed via signaling rtxes only,
|
||||
; and quiet comparisons must be expressed via quiet rtxes only.
|
||||
|
||||
; UNEQ a u== b -> !(a > b | b > a)
|
||||
; UNGT a u> b -> !!(b u< a)
|
||||
(define_expand "vec_cmpungt<mode>"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unlt:<tointvec> (match_operand:VFT 2 "register_operand" "v")
|
||||
(match_operand:VFT 1 "register_operand" "v"))))
|
||||
(set (match_dup 0)
|
||||
(not:<tointvec> (match_dup 0)))]
|
||||
"TARGET_VX")
|
||||
|
||||
; UNGE a u>= b -> !!(a u>= b)
|
||||
(define_expand "vec_cmpunge<mode>"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))))
|
||||
(set (match_dup 0)
|
||||
(not:<tointvec> (match_dup 0)))]
|
||||
"TARGET_VX")
|
||||
|
||||
; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a))
|
||||
(define_expand "vec_cmpuneq<mode>"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))
|
||||
(set (match_dup 3)
|
||||
(gt:<tointvec> (match_dup 2) (match_dup 1)))
|
||||
(set (match_dup 0) (ior:<tointvec> (match_dup 0) (match_dup 3)))
|
||||
(set (match_dup 0) (not:<tointvec> (match_dup 0)))]
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))))
|
||||
(set (match_dup 3)
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_dup 2)
|
||||
(match_dup 1))))
|
||||
(set (match_dup 0)
|
||||
(ior:<tointvec> (match_dup 0)
|
||||
(match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(not:<tointvec> (match_dup 0)))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (<tointvec>mode);
|
||||
|
|
@ -1499,18 +1604,24 @@
|
|||
(match_operand:VFT 2 "register_operand" "v")))
|
||||
(set (match_dup 3) (gt:<tointvec> (match_dup 2) (match_dup 1)))
|
||||
(set (match_dup 0) (ior:<tointvec> (match_dup 0) (match_dup 3)))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VXE"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (<tointvec>mode);
|
||||
})
|
||||
|
||||
; ORDERED (a, b): a >= b | b > a
|
||||
; ORDERED (a, b): !(a u< b) | !(a u>= b)
|
||||
(define_expand "vec_cmpordered<mode>"
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v")))
|
||||
(set (match_dup 3) (gt:<tointvec> (match_dup 2) (match_dup 1)))
|
||||
(set (match_dup 0) (ior:<tointvec> (match_dup 0) (match_dup 3)))]
|
||||
[(set (match_operand:<tointvec> 0 "register_operand" "=v")
|
||||
(not:<tointvec>
|
||||
(unlt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
|
||||
(match_operand:VFT 2 "register_operand" "v"))))
|
||||
(set (match_dup 3)
|
||||
(not:<tointvec>
|
||||
(unge:<tointvec> (match_dup 1)
|
||||
(match_dup 2))))
|
||||
(set (match_dup 0)
|
||||
(ior:<tointvec> (match_dup 0)
|
||||
(match_dup 3)))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (<tointvec>mode);
|
||||
|
|
@ -1530,7 +1641,7 @@
|
|||
})
|
||||
|
||||
(define_code_iterator VEC_CMP_EXPAND
|
||||
[uneq ltgt ordered unordered])
|
||||
[ungt unge uneq ltgt ordered unordered])
|
||||
|
||||
(define_expand "vec_cmp<code>"
|
||||
[(match_operand 0 "register_operand" "")
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2019-10-11 Ilya Leoshkevich <iii@linux.ibm.com>
|
||||
|
||||
* gcc.target/s390/vector/vec-scalar-cmp-1.c: Adjust
|
||||
expectations.
|
||||
|
||||
2019-10-11 Eric Botcazou <ebotcazou@adacore.com>
|
||||
|
||||
* gnat.dg/array38.adb: New test.
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ gt (double a, double b)
|
|||
return a > b;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */
|
||||
/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */
|
||||
|
||||
int
|
||||
ge (double a, double b)
|
||||
|
|
@ -45,7 +45,7 @@ ge (double a, double b)
|
|||
return a >= b;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */
|
||||
/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */
|
||||
|
||||
int
|
||||
lt (double a, double b)
|
||||
|
|
@ -56,7 +56,7 @@ lt (double a, double b)
|
|||
return a < b;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */
|
||||
/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */
|
||||
|
||||
int
|
||||
le (double a, double b)
|
||||
|
|
@ -67,4 +67,4 @@ le (double a, double b)
|
|||
return a <= b;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "le:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */
|
||||
/* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue