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RISC-V: Adjust the strided store testcases check times on options

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The vsse* dump check times changes on options (O2, O3) after we add
(mem:BLK (scratch)) to the define_insn of strided load.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Adjust
	the vsse check times based on optimization option.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-12-19 09:03:59 +08:00
parent 46194b9127
commit d063549217
3 changed files with 6 additions and 3 deletions
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3
gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
View file

@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(double)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
View file

@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(int64_t)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
View file

@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(uint64_t)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" } } } } */