re PR target/60525 (ICE: in final_scan_insn, at final.c:2952)
PR target/60525 * config/i386/i386.md (floathi<X87MODEF>2): Delete expander; rename define_insn from *floathi<X87MODEF>2_i387; allow nonimmediate_operand. (*floathi<X87MODEF>2_i387_with_temp): Remove. (floathi splitters): Remove. (float<SWI48x>xf2): New pattern. (float<SWI48><MODEF>2): Rename from float<SWI48x><X87MODEF>2. Drop code that tried to handle DImode for 32-bit, but which was excluded by the pattern's condition. Drop allocation of stack temporary. (*floatsi<MODEF>2_vector_mixed_with_temp): Remove. (*float<SWI48><MODEF>2_mixed_with_temp): Remove. (*float<SWI48><MODEF>2_mixed_interunit): Remove. (*float<SWI48><MODEF>2_mixed_nointerunit): Remove. (*floatsi<MODEF>2_vector_sse_with_temp): Remove. (*float<SWI48><MODEF>2_sse_with_temp): Remove. (*float<SWI48><MODEF>2_sse_interunit): Remove. (*float<SWI48><MODEF>2_sse_nointerunit): Remove. (*float<SWI48x><X87MODEF>2_i387_with_temp): Remove. (*float<SWI48x><X87MODEF>2_i387): Remove. (all float _with_temp splitters): Remove. (*float<SWI48x><MODEF>2_i387): New pattern. (*float<SWI48><MODEF>2_sse): New pattern. (float TARGET_USE_VECTOR_CONVERTS splitters): Merge them. (float TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters): Merge them. From-SVN: r208587
This commit is contained in:
Richard Henderson
Richard Henderson
parent
47b5d284dd
commit
cfce90ac4a
2 changed files with 99 additions and 401 deletions
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@ -1,3 +1,30 @@
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2014-03-14 Richard Henderson <rth@redhat.com>
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PR target/60525
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* config/i386/i386.md (floathi<X87MODEF>2): Delete expander; rename
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define_insn from *floathi<X87MODEF>2_i387; allow nonimmediate_operand.
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(*floathi<X87MODEF>2_i387_with_temp): Remove.
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(floathi splitters): Remove.
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(float<SWI48x>xf2): New pattern.
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(float<SWI48><MODEF>2): Rename from float<SWI48x><X87MODEF>2. Drop
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code that tried to handle DImode for 32-bit, but which was excluded
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by the pattern's condition. Drop allocation of stack temporary.
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(*floatsi<MODEF>2_vector_mixed_with_temp): Remove.
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(*float<SWI48><MODEF>2_mixed_with_temp): Remove.
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(*float<SWI48><MODEF>2_mixed_interunit): Remove.
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(*float<SWI48><MODEF>2_mixed_nointerunit): Remove.
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(*floatsi<MODEF>2_vector_sse_with_temp): Remove.
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(*float<SWI48><MODEF>2_sse_with_temp): Remove.
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(*float<SWI48><MODEF>2_sse_interunit): Remove.
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(*float<SWI48><MODEF>2_sse_nointerunit): Remove.
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(*float<SWI48x><X87MODEF>2_i387_with_temp): Remove.
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(*float<SWI48x><X87MODEF>2_i387): Remove.
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(all float _with_temp splitters): Remove.
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(*float<SWI48x><MODEF>2_i387): New pattern.
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(*float<SWI48><MODEF>2_sse): New pattern.
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(float TARGET_USE_VECTOR_CONVERTS splitters): Merge them.
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(float TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters): Merge them.
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2014-03-14 Jakub Jelinek <jakub@redhat.com>
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Marek Polacek <polacek@redhat.com>
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@ -4653,36 +4653,12 @@
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;; Conversion between fixed point and floating point.
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;; Even though we only accept memory inputs, the backend _really_
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;; wants to be able to do this between registers.
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;; wants to be able to do this between registers. Thankfully, LRA
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;; will fix this up for us during register allocation.
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(define_expand "floathi<mode>2"
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[(parallel [(set (match_operand:X87MODEF 0 "register_operand")
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(float:X87MODEF
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(match_operand:HI 1 "nonimmediate_operand")))
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(clobber (match_dup 2))])]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)"
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{
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operands[2] = assign_386_stack_local (HImode, SLOT_TEMP);
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})
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(define_insn "*floathi<mode>2_i387_with_temp"
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[(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
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(float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))
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(clobber (match_operand:HI 2 "memory_operand" "=X,m"))]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)"
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"#"
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[(set_attr "type" "fmov,multi")
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(set_attr "mode" "<MODE>")
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(set_attr "unit" "*,i387")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floathi<mode>2_i387"
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(define_insn "floathi<mode>2"
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[(set (match_operand:X87MODEF 0 "register_operand" "=f")
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(float:X87MODEF (match_operand:HI 1 "memory_operand" "m")))]
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(float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m")))]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)"
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@ -4691,50 +4667,31 @@
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(set_attr "mode" "<MODE>")
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(set_attr "fp_int_src" "true")])
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(define_split
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[(set (match_operand:X87MODEF 0 "register_operand")
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(float:X87MODEF (match_operand:HI 1 "register_operand")))
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(clobber (match_operand:HI 2 "memory_operand"))]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)
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&& reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
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(define_insn "float<SWI48x:mode>xf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(float:XF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))]
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"TARGET_80387"
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"fild%Z1\t%1"
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[(set_attr "type" "fmov")
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(set_attr "mode" "XF")
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(set_attr "fp_int_src" "true")])
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(define_split
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[(set (match_operand:X87MODEF 0 "register_operand")
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(float:X87MODEF (match_operand:HI 1 "memory_operand")))
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(clobber (match_operand:HI 2 "memory_operand"))]
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"TARGET_80387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)
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&& reload_completed"
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[(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
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(define_expand "float<SWI48x:mode><X87MODEF:mode>2"
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[(parallel [(set (match_operand:X87MODEF 0 "register_operand")
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(float:X87MODEF
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(match_operand:SWI48x 1 "nonimmediate_operand")))
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(clobber (match_dup 2))])]
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"TARGET_80387
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|| ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
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&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
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(define_expand "float<SWI48:mode><MODEF:mode>2"
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[(set (match_operand:MODEF 0 "register_operand")
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(float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)"
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{
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bool native_int = TARGET_64BIT || <SWI48x:MODE>mode != DImode;
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if (!(native_int
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&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
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&& !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode))
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if (!(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
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&& !X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48:MODE>mode))
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{
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rtx reg = gen_reg_rtx (XFmode);
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rtx (*insn)(rtx, rtx);
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emit_insn (gen_float<SWI48x:mode>xf2 (reg, operands[1]));
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emit_insn (gen_float<SWI48:mode>xf2 (reg, operands[1]));
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if (<X87MODEF:MODE>mode == SFmode)
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if (<MODEF:MODE>mode == SFmode)
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insn = gen_truncxfsf2;
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else if (<X87MODEF:MODE>mode == DFmode)
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else if (<MODEF:MODE>mode == DFmode)
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insn = gen_truncxfdf2;
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else
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gcc_unreachable ();
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@ -4742,83 +4699,22 @@
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emit_insn (insn (operands[0], reg));
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DONE;
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}
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/* Avoid store forwarding (partial memory) stall penalty
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by passing DImode value through XMM registers. */
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if (!native_int
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&& TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
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&& optimize_function_for_speed_p (cfun))
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{
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operands[2] = assign_386_stack_local (<SWI48x:MODE>mode, SLOT_TEMP);
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emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
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operands[1],
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operands[2]));
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DONE;
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}
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/* Notice when we'd convert directly from general registers. */
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if (native_int
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&& (TARGET_MIX_SSE_I387 || TARGET_SSE_MATH)
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&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode)
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&& (TARGET_INTER_UNIT_CONVERSIONS
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|| optimize_function_for_size_p (cfun)))
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{
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emit_insn (gen_rtx_SET
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(VOIDmode, operands[0],
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gen_rtx_FLOAT (<X87MODEF:MODE>mode, operands[1])));
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DONE;
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}
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operands[2] = assign_386_stack_local (<SWI48x:MODE>mode, SLOT_TEMP);
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})
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(define_insn "*floatsi<mode>2_vector_mixed_with_temp"
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[(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x,x")
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(float:MODEF
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(match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x")))
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(clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))]
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"TARGET_SSE2 && TARGET_MIX_SSE_I387
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&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
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"#"
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[(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
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(set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<ssevecmode>")
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(set_attr "unit" "*,i387,*,*,*")
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(set_attr "athlon_decode" "*,*,double,direct,double")
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(set_attr "amdfam10_decode" "*,*,vector,double,double")
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(set_attr "bdver1_decode" "*,*,double,direct,double")
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(set_attr "fp_int_src" "true")])
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(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_with_temp"
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[(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
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(float:MODEF
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(match_operand:SWI48 1 "nonimmediate_operand" "m,?r,r,m")))
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(clobber (match_operand:SWI48 2 "memory_operand" "=X,m,m,X"))]
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387"
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"#"
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[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
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(define_insn "*float<SWI48x:mode><MODEF:mode>2_i387"
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[(set (match_operand:MODEF 0 "register_operand" "=f")
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(float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))]
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"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)"
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"fild%Z1\t%1"
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[(set_attr "type" "fmov")
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(set_attr "mode" "<MODEF:MODE>")
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(set_attr "unit" "*,i387,*,*")
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(set_attr "athlon_decode" "*,*,double,direct")
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(set_attr "amdfam10_decode" "*,*,vector,double")
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(set_attr "bdver1_decode" "*,*,double,direct")
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(set_attr "fp_int_src" "true")])
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(define_split
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[(set (match_operand:MODEF 0 "register_operand")
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(float:MODEF (match_operand:SWI48 1 "register_operand")))
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(clobber (match_operand:SWI48 2 "memory_operand"))]
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
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&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
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&& reload_completed && SSE_REG_P (operands[0])"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (float:MODEF (match_dup 2)))])
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(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_interunit"
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(define_insn "*float<SWI48:mode><MODEF:mode>2_sse"
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[(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
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(float:MODEF
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(match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
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&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
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"@
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fild%Z1\t%1
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%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}
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@ -4836,289 +4732,64 @@
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(set_attr "athlon_decode" "*,double,direct")
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(set_attr "amdfam10_decode" "*,vector,double")
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(set_attr "bdver1_decode" "*,double,direct")
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(set_attr "fp_int_src" "true")])
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(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed_nointerunit"
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[(set (match_operand:MODEF 0 "register_operand" "=f,x")
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(float:MODEF
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(match_operand:SWI48 1 "memory_operand" "m,m")))]
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
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&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
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"@
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fild%Z1\t%1
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%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
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[(set_attr "type" "fmov,sseicvt")
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(set_attr "prefix" "orig,maybe_vex")
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(set_attr "mode" "<MODEF:MODE>")
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(set (attr "prefix_rex")
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(if_then_else
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(and (eq_attr "prefix" "maybe_vex")
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(match_test "<SWI48:MODE>mode == DImode"))
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(const_string "1")
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(const_string "*")))
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(set_attr "athlon_decode" "*,direct")
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(set_attr "amdfam10_decode" "*,double")
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(set_attr "bdver1_decode" "*,direct")
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(set_attr "fp_int_src" "true")])
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(define_insn "*floatsi<mode>2_vector_sse_with_temp"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,x")
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(float:MODEF
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(match_operand:SI 1 "nonimmediate_operand" "r,m,!x")))
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(clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))]
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"TARGET_SSE2 && TARGET_SSE_MATH
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&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
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"#"
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[(set_attr "type" "sseicvt")
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(set_attr "mode" "<MODE>,<MODE>,<ssevecmode>")
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(set_attr "athlon_decode" "double,direct,double")
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(set_attr "amdfam10_decode" "vector,double,double")
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(set_attr "bdver1_decode" "double,direct,double")
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(set_attr "fp_int_src" "true")])
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(define_split
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[(set (match_operand:MODEF 0 "register_operand")
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(float:MODEF (match_operand:SI 1 "register_operand")))
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(clobber (match_operand:SI 2 "memory_operand"))]
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"TARGET_SSE2 && TARGET_SSE_MATH
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&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
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&& reload_completed && SSE_REG_P (operands[0])"
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[(const_int 0)]
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{
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rtx op1 = operands[1];
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operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
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<MODE>mode, 0);
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if (GET_CODE (op1) == SUBREG)
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op1 = SUBREG_REG (op1);
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if (GENERAL_REG_P (op1) && TARGET_INTER_UNIT_MOVES_TO_VEC)
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{
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operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
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emit_insn (gen_sse2_loadld (operands[4],
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CONST0_RTX (V4SImode), operands[1]));
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}
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/* We can ignore possible trapping value in the
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high part of SSE register for non-trapping math. */
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else if (SSE_REG_P (op1) && !flag_trapping_math)
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operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
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else
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{
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operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
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emit_move_insn (operands[2], operands[1]);
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emit_insn (gen_sse2_loadld (operands[4],
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CONST0_RTX (V4SImode), operands[2]));
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}
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if (<ssevecmode>mode == V4SFmode)
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emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
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else
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emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
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DONE;
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})
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(define_split
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[(set (match_operand:MODEF 0 "register_operand")
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(float:MODEF (match_operand:SI 1 "memory_operand")))
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(clobber (match_operand:SI 2 "memory_operand"))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(const_int 0)]
|
||||
{
|
||||
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
|
||||
<MODE>mode, 0);
|
||||
operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
|
||||
|
||||
emit_insn (gen_sse2_loadld (operands[4],
|
||||
CONST0_RTX (V4SImode), operands[1]));
|
||||
if (<ssevecmode>mode == V4SFmode)
|
||||
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
|
||||
else
|
||||
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:MODEF 0 "register_operand")
|
||||
(float:MODEF (match_operand:SI 1 "memory_operand")))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(const_int 0)]
|
||||
{
|
||||
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
|
||||
<MODE>mode, 0);
|
||||
operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
|
||||
|
||||
emit_insn (gen_sse2_loadld (operands[4],
|
||||
CONST0_RTX (V4SImode), operands[1]));
|
||||
if (<ssevecmode>mode == V4SFmode)
|
||||
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
|
||||
else
|
||||
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "*float<SWI48:mode><MODEF:mode>2_sse_with_temp"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(float:MODEF
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "r,m")))
|
||||
(clobber (match_operand:SWI48 2 "memory_operand" "=m,X"))]
|
||||
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
|
||||
"#"
|
||||
[(set_attr "type" "sseicvt")
|
||||
(set_attr "mode" "<MODEF:MODE>")
|
||||
(set_attr "athlon_decode" "double,direct")
|
||||
(set_attr "amdfam10_decode" "vector,double")
|
||||
(set_attr "bdver1_decode" "double,direct")
|
||||
(set_attr "btver2_decode" "double,double")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_insn "*float<SWI48:mode><MODEF:mode>2_sse_interunit"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(float:MODEF
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "r,m")))]
|
||||
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
|
||||
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
|
||||
"%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
|
||||
[(set_attr "type" "sseicvt")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "<MODEF:MODE>")
|
||||
(set (attr "prefix_rex")
|
||||
(if_then_else
|
||||
(and (eq_attr "prefix" "maybe_vex")
|
||||
(match_test "<SWI48:MODE>mode == DImode"))
|
||||
(const_string "1")
|
||||
(const_string "*")))
|
||||
(set_attr "athlon_decode" "double,direct")
|
||||
(set_attr "amdfam10_decode" "vector,double")
|
||||
(set_attr "bdver1_decode" "double,direct")
|
||||
(set_attr "btver2_decode" "double,double")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:MODEF 0 "register_operand")
|
||||
(float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))
|
||||
(clobber (match_operand:SWI48 2 "memory_operand"))]
|
||||
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
|
||||
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
|
||||
|
||||
(define_insn "*float<SWI48:mode><MODEF:mode>2_sse_nointerunit"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(float:MODEF
|
||||
(match_operand:SWI48 1 "memory_operand" "m")))]
|
||||
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
|
||||
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
|
||||
"%vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
|
||||
[(set_attr "type" "sseicvt")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "<MODEF:MODE>")
|
||||
(set (attr "prefix_rex")
|
||||
(if_then_else
|
||||
(and (eq_attr "prefix" "maybe_vex")
|
||||
(match_test "<SWI48:MODE>mode == DImode"))
|
||||
(const_string "1")
|
||||
(const_string "*")))
|
||||
(set_attr "athlon_decode" "direct")
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "bdver1_decode" "direct")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:MODEF 0 "register_operand")
|
||||
(float:MODEF (match_operand:SWI48 1 "register_operand")))
|
||||
(clobber (match_operand:SWI48 2 "memory_operand"))]
|
||||
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
|
||||
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(set (match_dup 0) (float:MODEF (match_dup 2)))])
|
||||
|
||||
(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"
|
||||
[(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
|
||||
(float:X87MODEF
|
||||
(match_operand:SWI48x 1 "nonimmediate_operand" "m,?r")))
|
||||
(clobber (match_operand:SWI48x 2 "memory_operand" "=X,m"))]
|
||||
"TARGET_80387
|
||||
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
|
||||
"@
|
||||
fild%Z1\t%1
|
||||
#"
|
||||
[(set_attr "type" "fmov,multi")
|
||||
(set_attr "mode" "<X87MODEF:MODE>")
|
||||
(set_attr "unit" "*,i387")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387"
|
||||
[(set (match_operand:X87MODEF 0 "register_operand" "=f")
|
||||
(float:X87MODEF
|
||||
(match_operand:SWI48x 1 "memory_operand" "m")))]
|
||||
"TARGET_80387
|
||||
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
|
||||
"fild%Z1\t%1"
|
||||
[(set_attr "type" "fmov")
|
||||
(set_attr "mode" "<X87MODEF:MODE>")
|
||||
(set_attr "fp_int_src" "true")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:X87MODEF 0 "fp_register_operand")
|
||||
(float:X87MODEF (match_operand:SWI48x 1 "register_operand")))
|
||||
(clobber (match_operand:SWI48x 2 "memory_operand"))]
|
||||
"TARGET_80387
|
||||
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
|
||||
&& reload_completed"
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:X87MODEF 0 "fp_register_operand")
|
||||
(float:X87MODEF (match_operand:SWI48x 1 "memory_operand")))
|
||||
(clobber (match_operand:SWI48x 2 "memory_operand"))]
|
||||
"TARGET_80387
|
||||
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
|
||||
&& reload_completed"
|
||||
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
|
||||
|
||||
;; Avoid partial SSE register dependency stalls
|
||||
(set_attr "fp_int_src" "true")
|
||||
(set (attr "enabled")
|
||||
(cond [(eq_attr "alternative" "0")
|
||||
(symbol_ref "TARGET_MIX_SSE_I387")
|
||||
(eq_attr "alternative" "1")
|
||||
(symbol_ref "TARGET_INTER_UNIT_CONVERSIONS
|
||||
|| optimize_function_for_size_p (cfun)")
|
||||
]
|
||||
(symbol_ref "true")))
|
||||
])
|
||||
|
||||
;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory
|
||||
;; slots when !TARGET_INTER_UNIT_MOVES_TO_VEC disables the general_regs
|
||||
;; alternative in sse2_loadld.
|
||||
(define_split
|
||||
[(set (match_operand:MODEF 0 "register_operand")
|
||||
(float:MODEF (match_operand:SI 1 "nonimmediate_operand")))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& TARGET_SSE_PARTIAL_REG_DEPENDENCY
|
||||
&& optimize_function_for_speed_p (cfun)
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(set (match_dup 0)
|
||||
(vec_merge:<ssevecmode>
|
||||
(vec_duplicate:<ssevecmode>
|
||||
(float:MODEF (match_dup 1)))
|
||||
(match_dup 0)
|
||||
(const_int 1)))]
|
||||
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
|
||||
&& reload_completed && SSE_REG_P (operands[0])
|
||||
&& (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)"
|
||||
[(const_int 0)]
|
||||
{
|
||||
operands[0] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
|
||||
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
|
||||
<MODE>mode, 0);
|
||||
emit_move_insn (operands[0], CONST0_RTX (<ssevecmode>mode));
|
||||
operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
|
||||
|
||||
emit_insn (gen_sse2_loadld (operands[4],
|
||||
CONST0_RTX (V4SImode), operands[1]));
|
||||
|
||||
if (<ssevecmode>mode == V4SFmode)
|
||||
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
|
||||
else
|
||||
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Avoid partial SSE register dependency stalls
|
||||
(define_split
|
||||
[(set (match_operand:MODEF 0 "register_operand")
|
||||
(float:MODEF (match_operand:DI 1 "nonimmediate_operand")))]
|
||||
"TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
|
||||
(float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& TARGET_SSE_PARTIAL_REG_DEPENDENCY
|
||||
&& optimize_function_for_speed_p (cfun)
|
||||
&& reload_completed && SSE_REG_P (operands[0])"
|
||||
[(set (match_dup 0)
|
||||
(vec_merge:<ssevecmode>
|
||||
(vec_duplicate:<ssevecmode>
|
||||
(float:MODEF (match_dup 1)))
|
||||
(match_dup 0)
|
||||
(const_int 1)))]
|
||||
[(const_int 0)]
|
||||
{
|
||||
operands[0] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
|
||||
<MODE>mode, 0);
|
||||
emit_move_insn (operands[0], CONST0_RTX (<ssevecmode>mode));
|
||||
const enum machine_mode vmode = <MODEF:ssevecmode>mode;
|
||||
const enum machine_mode mode = <MODEF:MODE>mode;
|
||||
rtx t, op0 = simplify_gen_subreg (vmode, operands[0], mode, 0);
|
||||
|
||||
emit_move_insn (op0, CONST0_RTX (vmode));
|
||||
|
||||
t = gen_rtx_FLOAT (mode, operands[1]);
|
||||
t = gen_rtx_VEC_DUPLICATE (vmode, t);
|
||||
t = gen_rtx_VEC_MERGE (vmode, t, op0, const1_rtx);
|
||||
emit_insn (gen_rtx_SET (VOIDmode, op0, t));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Break partial reg stall for cvtsd2ss.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue