xtensa: drop unimplemented floating point operations

xtensa ISA never implemented FP division, reciprocal, square root and
inverse square root as single opcode. Remove patterns that can emit
them.

2014-10-09  Max Filippov  <jcmvbkbc@gmail.com>

gcc/
    * config/xtensa/xtensa.md (divsf3, *recipsf2, sqrtsf2, *rsqrtsf2):
    remove.

From-SVN: r216233
This commit is contained in:
Max Filippov 2014-10-15 04:17:30 +00:00 committed by Max Filippov
parent 5d12b7688f
commit cf14ea9fe3
2 changed files with 6 additions and 43 deletions

View file

@ -1,3 +1,8 @@
2014-10-14 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa.md (divsf3, *recipsf2, sqrtsf2, *rsqrtsf2):
remove.
2014-10-14 Andrew Pinski <apinski@cavium.com>
* explow.c (convert_memory_address_addr_space): Rename to ...

View file

@ -82,7 +82,7 @@
;; Attributes.
(define_attr "type"
"unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fdiv,fsqrt,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr,entry"
"unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr,entry"
(const_string "unknown"))
(define_attr "mode"
@ -360,26 +360,6 @@
(set_attr "mode" "SI")
(set_attr "length" "3")])
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT_DIV"
"div.s\t%0, %1, %2"
[(set_attr "type" "fdiv")
(set_attr "mode" "SF")
(set_attr "length" "3")])
(define_insn "*recipsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT_RECIP && flag_unsafe_math_optimizations"
"recip.s\t%0, %2"
[(set_attr "type" "fdiv")
(set_attr "mode" "SF")
(set_attr "length" "3")])
;; Remainders.
@ -403,28 +383,6 @@
(set_attr "mode" "SI")
(set_attr "length" "3")])
;; Square roots.
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT_SQRT"
"sqrt.s\t%0, %1"
[(set_attr "type" "fsqrt")
(set_attr "mode" "SF")
(set_attr "length" "3")])
(define_insn "*rsqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
"TARGET_HARD_FLOAT_RSQRT && flag_unsafe_math_optimizations"
"rsqrt.s\t%0, %2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "SF")
(set_attr "length" "3")])
;; Absolute value.