LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm vector
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint on the shift range.
gcc/ChangeLog:
* config/loongarch/constraints.md (Uuv6, Uuvx): Remove Uuv6,
add Uuvx as replicated vector const with unsigned range [0,umax].
* config/loongarch/lasx.md (xvsrl, xvsra, xvsll): Mask shift
offset by its unit bits.
* config/loongarch/lsx.md (vsrl, vsra, vsll): Likewise.
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_same_int_p): Set default for low and high.
* config/loongarch/predicates.md: Replace reg_or_vector_same_uimm6
_operand to reg_or_vector_same_uimm_operand.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c: New test.
This commit is contained in:
Jinyang He
Lulu Cheng
parent
4ad1c87ad2
commit
cd107c1603
7 changed files with 254 additions and 37 deletions
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@ -334,19 +334,19 @@
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(and (match_code "const_vector")
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(match_test "loongarch_const_vector_same_int_p (op, mode, -16, 15)")))
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(define_constraint "Uuv6"
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"@internal
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A replicated vector const in which the replicated value is in the range
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[0,63]."
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(and (match_code "const_vector")
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(match_test "loongarch_const_vector_same_int_p (op, mode, 0, 63)")))
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(define_constraint "Urv8"
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"@internal
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A replicated vector const with replicated byte values as well as elements"
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(and (match_code "const_vector")
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(match_test "loongarch_const_vector_same_bytes_p (op, mode)")))
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(define_constraint "Uuvx"
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"@internal
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A replicated vector const in which the replicated value is in the unsigned
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range [0,umax]."
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(and (match_code "const_vector")
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(match_test "loongarch_const_vector_same_int_p (op, mode)")))
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(define_memory_constraint "ZC"
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"A memory operand whose address is formed by a base register and offset
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that is suitable for use in instructions with the same addressing mode
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@ -1013,11 +1013,23 @@
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[(set (match_operand:ILASX 0 "register_operand" "=f,f")
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(lshiftrt:ILASX
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(match_operand:ILASX 1 "register_operand" "f,f")
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(match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LASX"
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"@
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xvsrl.<lasxfmt>\t%u0,%u1,%u2
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xvsrli.<lasxfmt>\t%u0,%u1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "xvsrl.<lasxfmt>\t%u0,%u1,%u2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "xvsrli.<lasxfmt>\t%u0,%u1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -1026,11 +1038,23 @@
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[(set (match_operand:ILASX 0 "register_operand" "=f,f")
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(ashiftrt:ILASX
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(match_operand:ILASX 1 "register_operand" "f,f")
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(match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LASX"
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"@
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xvsra.<lasxfmt>\t%u0,%u1,%u2
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xvsrai.<lasxfmt>\t%u0,%u1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "xvsra.<lasxfmt>\t%u0,%u1,%u2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "xvsrai.<lasxfmt>\t%u0,%u1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -1039,11 +1063,23 @@
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[(set (match_operand:ILASX 0 "register_operand" "=f,f")
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(ashift:ILASX
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(match_operand:ILASX 1 "register_operand" "f,f")
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(match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LASX"
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"@
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xvsll.<lasxfmt>\t%u0,%u1,%u2
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xvslli.<lasxfmt>\t%u0,%u1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "xvsll.<lasxfmt>\t%u0,%u1,%u2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "xvslli.<lasxfmt>\t%u0,%u1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -113,8 +113,9 @@ extern rtx loongarch_return_addr (int, rtx);
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extern bool loongarch_const_vector_same_val_p (rtx, machine_mode);
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extern bool loongarch_const_vector_same_bytes_p (rtx, machine_mode);
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extern bool loongarch_const_vector_same_int_p (rtx, machine_mode, HOST_WIDE_INT,
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HOST_WIDE_INT);
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extern bool loongarch_const_vector_same_int_p (rtx, machine_mode,
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HOST_WIDE_INT low = HOST_WIDE_INT_MIN,
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HOST_WIDE_INT high = HOST_WIDE_INT_MAX);
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extern bool loongarch_const_vector_shuffle_set_p (rtx, machine_mode);
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extern bool loongarch_const_vector_bitimm_set_p (rtx, machine_mode);
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extern bool loongarch_const_vector_bitimm_clr_p (rtx, machine_mode);
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@ -879,11 +879,23 @@
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[(set (match_operand:ILSX 0 "register_operand" "=f,f")
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(lshiftrt:ILSX
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(match_operand:ILSX 1 "register_operand" "f,f")
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(match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LSX"
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"@
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vsrl.<lsxfmt>\t%w0,%w1,%w2
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vsrli.<lsxfmt>\t%w0,%w1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "vsrl.<lsxfmt>\t%w0,%w1,%w2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "vsrli.<lsxfmt>\t%w0,%w1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -891,11 +903,23 @@
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[(set (match_operand:ILSX 0 "register_operand" "=f,f")
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(ashiftrt:ILSX
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(match_operand:ILSX 1 "register_operand" "f,f")
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(match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LSX"
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"@
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vsra.<lsxfmt>\t%w0,%w1,%w2
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vsrai.<lsxfmt>\t%w0,%w1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "vsra.<lsxfmt>\t%w0,%w1,%w2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "vsrai.<lsxfmt>\t%w0,%w1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -903,11 +927,23 @@
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[(set (match_operand:ILSX 0 "register_operand" "=f,f")
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(ashift:ILSX
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(match_operand:ILSX 1 "register_operand" "f,f")
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(match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
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(match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))]
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"ISA_HAS_LSX"
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"@
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vsll.<lsxfmt>\t%w0,%w1,%w2
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vslli.<lsxfmt>\t%w0,%w1,%E2"
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{
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switch (which_alternative)
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{
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case 0:
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return "vsll.<lsxfmt>\t%w0,%w1,%w2";
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case 1:
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{
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unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0));
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operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1));
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return "vslli.<lsxfmt>\t%w0,%w1,%d2";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "simd_shift")
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(set_attr "mode" "<MODE>")])
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@ -635,10 +635,10 @@
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return loongarch_const_vector_same_int_p (op, mode, -31, 31);
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})
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(define_predicate "const_vector_same_uimm6_operand"
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(define_predicate "const_vector_same_uimm_operand"
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(match_code "const_vector")
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{
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return loongarch_const_vector_same_int_p (op, mode, 0, 63);
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return loongarch_const_vector_same_int_p (op, mode);
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})
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(define_predicate "par_const_vector_shf_set_operand"
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@ -663,6 +663,6 @@
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "const_vector_same_ximm5_operand")))
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(define_predicate "reg_or_vector_same_uimm6_operand"
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(define_predicate "reg_or_vector_same_uimm_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "const_vector_same_uimm6_operand")))
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(match_operand 0 "const_vector_same_uimm_operand")))
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@ -0,0 +1,72 @@
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/* Test shift bits overflow in vector */
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/* { dg-do assemble } */
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/* { dg-options "-mlasx -O2 -save-temps" } */
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/* { dg-final { scan-assembler "xvslli.b.*,1" } } */
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/* { dg-final { scan-assembler "xvslli.b.*,7" } } */
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/* { dg-final { scan-assembler "xvslli.h.*,1" } } */
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/* { dg-final { scan-assembler "xvslli.h.*,15" } } */
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/* { dg-final { scan-assembler "xvslli.w.*,1" } } */
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/* { dg-final { scan-assembler "xvslli.w.*,31" } } */
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/* { dg-final { scan-assembler "xvslli.d.*,1" } } */
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/* { dg-final { scan-assembler "xvslli.d.*,63" } } */
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/* { dg-final { scan-assembler "xvsrli.b.*,1" } } */
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/* { dg-final { scan-assembler "xvsrli.b.*,7" } } */
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/* { dg-final { scan-assembler "xvsrli.h.*,1" } } */
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/* { dg-final { scan-assembler "xvsrli.h.*,15" } } */
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/* { dg-final { scan-assembler "xvsrli.w.*,1" } } */
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/* { dg-final { scan-assembler "xvsrli.w.*,31" } } */
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/* { dg-final { scan-assembler "xvsrli.d.*,1" } } */
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/* { dg-final { scan-assembler "xvsrli.d.*,63" } } */
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/* { dg-final { scan-assembler "xvsrai.b.*,1" } } */
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/* { dg-final { scan-assembler "xvsrai.b.*,7" } } */
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/* { dg-final { scan-assembler "xvsrai.h.*,1" } } */
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/* { dg-final { scan-assembler "xvsrai.h.*,15" } } */
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/* { dg-final { scan-assembler "xvsrai.w.*,1" } } */
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/* { dg-final { scan-assembler "xvsrai.w.*,31" } } */
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/* { dg-final { scan-assembler "xvsrai.d.*,1" } } */
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/* { dg-final { scan-assembler "xvsrai.d.*,63" } } */
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typedef signed char v32i8 __attribute__ ((vector_size (32), aligned (32)));
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typedef short v16i16 __attribute__ ((vector_size (32), aligned (32)));
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typedef int v8i32 __attribute__ ((vector_size (32), aligned (32)));
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typedef long long v4i64 __attribute__ ((vector_size (32), aligned (32)));
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#define TWICE(_) _, _
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#define V32I8_RVAL(_) (v32i8) {TWICE(TWICE(TWICE(TWICE(TWICE(_)))))}
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#define V16I16_RVAL(_) (v16i16) {TWICE(TWICE(TWICE(TWICE(_))))}
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#define V8I32_RVAL(_) (v8i32) {TWICE(TWICE(TWICE(_)))}
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#define V4I64_RVAL(_) (v4i64) {TWICE(TWICE(_))}
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#define TEST_FUNC(typ, key, inst, rept, val) \
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typ \
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_##key##inst (typ _) \
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{ \
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return __builtin_lasx_##inst(_, rept(val)); \
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}
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TEST_FUNC(v32i8, pos, xvsll_b, V32I8_RVAL, 65)
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TEST_FUNC(v32i8, neg, xvsll_b, V32I8_RVAL, -65)
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TEST_FUNC(v16i16, pos, xvsll_h, V16I16_RVAL, 65)
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TEST_FUNC(v16i16, neg, xvsll_h, V16I16_RVAL, -65)
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TEST_FUNC(v8i32, pos, xvsll_w, V8I32_RVAL, 65)
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TEST_FUNC(v8i32, neg, xvsll_w, V8I32_RVAL, -65)
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TEST_FUNC(v4i64, pos, xvsll_d, V4I64_RVAL, 65)
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TEST_FUNC(v4i64, neg, xvsll_d, V4I64_RVAL, -65)
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TEST_FUNC(v32i8, pos, xvsrl_b, V32I8_RVAL, 65)
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TEST_FUNC(v32i8, neg, xvsrl_b, V32I8_RVAL, -65)
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TEST_FUNC(v16i16, pos, xvsrl_h, V16I16_RVAL, 65)
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TEST_FUNC(v16i16, neg, xvsrl_h, V16I16_RVAL, -65)
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TEST_FUNC(v8i32, pos, xvsrl_w, V8I32_RVAL, 65)
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TEST_FUNC(v8i32, neg, xvsrl_w, V8I32_RVAL, -65)
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TEST_FUNC(v4i64, pos, xvsrl_d, V4I64_RVAL, 65)
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TEST_FUNC(v4i64, neg, xvsrl_d, V4I64_RVAL, -65)
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TEST_FUNC(v32i8, pos, xvsra_b, V32I8_RVAL, 65)
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TEST_FUNC(v32i8, neg, xvsra_b, V32I8_RVAL, -65)
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TEST_FUNC(v16i16, pos, xvsra_h, V16I16_RVAL, 65)
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TEST_FUNC(v16i16, neg, xvsra_h, V16I16_RVAL, -65)
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TEST_FUNC(v8i32, pos, xvsra_w, V8I32_RVAL, 65)
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TEST_FUNC(v8i32, neg, xvsra_w, V8I32_RVAL, -65)
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TEST_FUNC(v4i64, pos, xvsra_d, V4I64_RVAL, 65)
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TEST_FUNC(v4i64, neg, xvsra_d, V4I64_RVAL, -65)
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@ -0,0 +1,72 @@
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/* Test shift bits overflow in vector */
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/* { dg-do assemble } */
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/* { dg-options "-mlsx -O2 -save-temps" } */
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/* { dg-final { scan-assembler "vslli.b.*,1" } } */
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/* { dg-final { scan-assembler "vslli.b.*,7" } } */
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/* { dg-final { scan-assembler "vslli.h.*,1" } } */
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/* { dg-final { scan-assembler "vslli.h.*,15" } } */
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/* { dg-final { scan-assembler "vslli.w.*,1" } } */
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/* { dg-final { scan-assembler "vslli.w.*,31" } } */
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/* { dg-final { scan-assembler "vslli.d.*,1" } } */
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/* { dg-final { scan-assembler "vslli.d.*,63" } } */
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/* { dg-final { scan-assembler "vsrli.b.*,1" } } */
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/* { dg-final { scan-assembler "vsrli.b.*,7" } } */
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/* { dg-final { scan-assembler "vsrli.h.*,1" } } */
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/* { dg-final { scan-assembler "vsrli.h.*,15" } } */
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/* { dg-final { scan-assembler "vsrli.w.*,1" } } */
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/* { dg-final { scan-assembler "vsrli.w.*,31" } } */
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/* { dg-final { scan-assembler "vsrli.d.*,1" } } */
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/* { dg-final { scan-assembler "vsrli.d.*,63" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.b.*,1" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.b.*,7" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.h.*,1" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.h.*,15" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.w.*,1" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.w.*,31" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.d.*,1" } } */
|
||||
/* { dg-final { scan-assembler "vsrai.d.*,63" } } */
|
||||
|
||||
typedef signed char v16i8 __attribute__ ((vector_size (16), aligned (16)));
|
||||
typedef short v8i16 __attribute__ ((vector_size (16), aligned (16)));
|
||||
typedef int v4i32 __attribute__ ((vector_size (16), aligned (16)));
|
||||
typedef long long v2i64 __attribute__ ((vector_size (16), aligned (16)));
|
||||
|
||||
#define TWICE(_) _, _
|
||||
#define V16I8_RVAL(_) (v16i8) {TWICE(TWICE(TWICE(TWICE(_))))}
|
||||
#define V8I16_RVAL(_) (v8i16) {TWICE(TWICE(TWICE(_)))}
|
||||
#define V4I32_RVAL(_) (v4i32) {TWICE(TWICE(_))}
|
||||
#define V2I64_RVAL(_) (v2i64) {TWICE(_)}
|
||||
|
||||
#define TEST_FUNC(typ, key, inst, rept, val) \
|
||||
typ \
|
||||
_##key##inst (typ _) \
|
||||
{ \
|
||||
return __builtin_lsx_##inst(_, rept(val)); \
|
||||
}
|
||||
|
||||
TEST_FUNC(v16i8, pos, vsll_b, V16I8_RVAL, 65)
|
||||
TEST_FUNC(v16i8, neg, vsll_b, V16I8_RVAL, -65)
|
||||
TEST_FUNC(v8i16, pos, vsll_h, V8I16_RVAL, 65)
|
||||
TEST_FUNC(v8i16, neg, vsll_h, V8I16_RVAL, -65)
|
||||
TEST_FUNC(v4i32, pos, vsll_w, V4I32_RVAL, 65)
|
||||
TEST_FUNC(v4i32, neg, vsll_w, V4I32_RVAL, -65)
|
||||
TEST_FUNC(v2i64, pos, vsll_d, V2I64_RVAL, 65)
|
||||
TEST_FUNC(v2i64, neg, vsll_d, V2I64_RVAL, -65)
|
||||
|
||||
TEST_FUNC(v16i8, pos, vsrl_b, V16I8_RVAL, 65)
|
||||
TEST_FUNC(v16i8, neg, vsrl_b, V16I8_RVAL, -65)
|
||||
TEST_FUNC(v8i16, pos, vsrl_h, V8I16_RVAL, 65)
|
||||
TEST_FUNC(v8i16, neg, vsrl_h, V8I16_RVAL, -65)
|
||||
TEST_FUNC(v4i32, pos, vsrl_w, V4I32_RVAL, 65)
|
||||
TEST_FUNC(v4i32, neg, vsrl_w, V4I32_RVAL, -65)
|
||||
TEST_FUNC(v2i64, pos, vsrl_d, V2I64_RVAL, 65)
|
||||
TEST_FUNC(v2i64, neg, vsrl_d, V2I64_RVAL, -65)
|
||||
|
||||
TEST_FUNC(v16i8, pos, vsra_b, V16I8_RVAL, 65)
|
||||
TEST_FUNC(v16i8, neg, vsra_b, V16I8_RVAL, -65)
|
||||
TEST_FUNC(v8i16, pos, vsra_h, V8I16_RVAL, 65)
|
||||
TEST_FUNC(v8i16, neg, vsra_h, V8I16_RVAL, -65)
|
||||
TEST_FUNC(v4i32, pos, vsra_w, V4I32_RVAL, 65)
|
||||
TEST_FUNC(v4i32, neg, vsra_w, V4I32_RVAL, -65)
|
||||
TEST_FUNC(v2i64, pos, vsra_d, V2I64_RVAL, 65)
|
||||
TEST_FUNC(v2i64, neg, vsra_d, V2I64_RVAL, -65)
|
||||
Loading…
Add table
Reference in a new issue