[AARCH64] Add zip{1, 2}, uzp{1, 2}, trn{1, 2} support
for vector permute. gcc/ * config/aarch64/aarch64-simd-builtins.def: Add new builtins. * config/aarch64/aarch64-simd.md (simd_type): Add uzp. (aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): New. * config/aarch64/aarch64.c (aarch64_evpc_trn): New. (aarch64_evpc_uzp): Likewise. (aarch64_evpc_zip): Likewise. (aarch64_expand_vec_perm_const_1): Check for trn, zip, uzp patterns. * config/aarch64/iterators.md (unspec): Add neccessary unspecs. (PERMUTE): New. (perm_insn): Likewise. (perm_hilo): Likewise. From-SVN: r194219
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
88b080739a
commit
cc4d934fa0
5 changed files with 317 additions and 2 deletions
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@ -1,3 +1,17 @@
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2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd-builtins.def: Add new builtins.
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* config/aarch64/aarch64-simd.md (simd_type): Add uzp.
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(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): New.
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* config/aarch64/aarch64.c (aarch64_evpc_trn): New.
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(aarch64_evpc_uzp): Likewise.
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(aarch64_evpc_zip): Likewise.
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(aarch64_expand_vec_perm_const_1): Check for trn, zip, uzp patterns.
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* config/aarch64/iterators.md (unspec): Add neccessary unspecs.
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(PERMUTE): New.
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(perm_insn): Likewise.
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(perm_hilo): Likewise.
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2012-12-05 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-protos.h
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@ -224,3 +224,12 @@
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BUILTIN_VDQF (UNOP, fcvtpu)
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BUILTIN_VDQF (UNOP, fcvtms)
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BUILTIN_VDQF (UNOP, fcvtmu)
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/* Implemented by
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aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
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BUILTIN_VALL (BINOP, zip1)
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BUILTIN_VALL (BINOP, zip2)
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BUILTIN_VALL (BINOP, uzp1)
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BUILTIN_VALL (BINOP, uzp2)
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BUILTIN_VALL (BINOP, trn1)
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BUILTIN_VALL (BINOP, trn2)
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@ -128,7 +128,8 @@
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; simd_store4s store single structure from one lane for four registers (ST4 [index]).
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; simd_tbl table lookup.
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; simd_trn transpose.
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; simd_zip zip/unzip.
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; simd_uzp unzip.
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; simd_zip zip.
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(define_attr "simd_type"
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"simd_abd,\
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@ -230,6 +231,7 @@
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simd_store4s,\
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simd_tbl,\
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simd_trn,\
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simd_uzp,\
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simd_zip,\
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none"
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(const_string "none"))
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@ -3406,6 +3408,17 @@
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DONE;
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})
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(define_insn "aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>"
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[(set (match_operand:VALL 0 "register_operand" "=w")
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(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
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(match_operand:VALL 2 "register_operand" "w")]
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PERMUTE))]
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"TARGET_SIMD"
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"<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "simd_type" "simd_<PERMUTE:perm_insn>")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_st2<mode>_dreg"
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[(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:TI [(match_operand:OI 1 "register_operand" "w")
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@ -6919,6 +6919,261 @@ aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
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aarch64_expand_vec_perm_1 (target, op0, op1, sel);
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}
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/* Recognize patterns suitable for the TRN instructions. */
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static bool
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aarch64_evpc_trn (struct expand_vec_perm_d *d)
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{
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unsigned int i, odd, mask, nelt = d->nelt;
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rtx out, in0, in1, x;
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rtx (*gen) (rtx, rtx, rtx);
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enum machine_mode vmode = d->vmode;
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if (GET_MODE_UNIT_SIZE (vmode) > 8)
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return false;
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/* Note that these are little-endian tests.
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We correct for big-endian later. */
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if (d->perm[0] == 0)
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odd = 0;
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else if (d->perm[0] == 1)
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odd = 1;
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else
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return false;
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mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
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for (i = 0; i < nelt; i += 2)
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{
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if (d->perm[i] != i + odd)
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return false;
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if (d->perm[i + 1] != ((i + nelt + odd) & mask))
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return false;
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}
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/* Success! */
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if (d->testing_p)
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return true;
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in0 = d->op0;
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in1 = d->op1;
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if (BYTES_BIG_ENDIAN)
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{
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x = in0, in0 = in1, in1 = x;
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odd = !odd;
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}
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out = d->target;
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if (odd)
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_trn2v16qi; break;
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case V8QImode: gen = gen_aarch64_trn2v8qi; break;
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case V8HImode: gen = gen_aarch64_trn2v8hi; break;
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case V4HImode: gen = gen_aarch64_trn2v4hi; break;
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case V4SImode: gen = gen_aarch64_trn2v4si; break;
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case V2SImode: gen = gen_aarch64_trn2v2si; break;
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case V2DImode: gen = gen_aarch64_trn2v2di; break;
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case V4SFmode: gen = gen_aarch64_trn2v4sf; break;
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case V2SFmode: gen = gen_aarch64_trn2v2sf; break;
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case V2DFmode: gen = gen_aarch64_trn2v2df; break;
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default:
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return false;
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}
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}
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else
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_trn1v16qi; break;
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case V8QImode: gen = gen_aarch64_trn1v8qi; break;
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case V8HImode: gen = gen_aarch64_trn1v8hi; break;
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case V4HImode: gen = gen_aarch64_trn1v4hi; break;
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case V4SImode: gen = gen_aarch64_trn1v4si; break;
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case V2SImode: gen = gen_aarch64_trn1v2si; break;
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case V2DImode: gen = gen_aarch64_trn1v2di; break;
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case V4SFmode: gen = gen_aarch64_trn1v4sf; break;
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case V2SFmode: gen = gen_aarch64_trn1v2sf; break;
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case V2DFmode: gen = gen_aarch64_trn1v2df; break;
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default:
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return false;
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}
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}
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emit_insn (gen (out, in0, in1));
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return true;
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}
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/* Recognize patterns suitable for the UZP instructions. */
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static bool
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aarch64_evpc_uzp (struct expand_vec_perm_d *d)
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{
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unsigned int i, odd, mask, nelt = d->nelt;
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rtx out, in0, in1, x;
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rtx (*gen) (rtx, rtx, rtx);
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enum machine_mode vmode = d->vmode;
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if (GET_MODE_UNIT_SIZE (vmode) > 8)
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return false;
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/* Note that these are little-endian tests.
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We correct for big-endian later. */
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if (d->perm[0] == 0)
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odd = 0;
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else if (d->perm[0] == 1)
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odd = 1;
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else
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return false;
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mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
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for (i = 0; i < nelt; i++)
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{
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unsigned elt = (i * 2 + odd) & mask;
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if (d->perm[i] != elt)
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return false;
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}
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/* Success! */
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if (d->testing_p)
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return true;
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in0 = d->op0;
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in1 = d->op1;
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if (BYTES_BIG_ENDIAN)
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{
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x = in0, in0 = in1, in1 = x;
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odd = !odd;
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}
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out = d->target;
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if (odd)
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_uzp2v16qi; break;
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case V8QImode: gen = gen_aarch64_uzp2v8qi; break;
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case V8HImode: gen = gen_aarch64_uzp2v8hi; break;
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case V4HImode: gen = gen_aarch64_uzp2v4hi; break;
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case V4SImode: gen = gen_aarch64_uzp2v4si; break;
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case V2SImode: gen = gen_aarch64_uzp2v2si; break;
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case V2DImode: gen = gen_aarch64_uzp2v2di; break;
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case V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
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case V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
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case V2DFmode: gen = gen_aarch64_uzp2v2df; break;
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default:
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return false;
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}
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}
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else
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_uzp1v16qi; break;
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case V8QImode: gen = gen_aarch64_uzp1v8qi; break;
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case V8HImode: gen = gen_aarch64_uzp1v8hi; break;
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case V4HImode: gen = gen_aarch64_uzp1v4hi; break;
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case V4SImode: gen = gen_aarch64_uzp1v4si; break;
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case V2SImode: gen = gen_aarch64_uzp1v2si; break;
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case V2DImode: gen = gen_aarch64_uzp1v2di; break;
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case V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
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case V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
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case V2DFmode: gen = gen_aarch64_uzp1v2df; break;
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default:
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return false;
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}
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}
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emit_insn (gen (out, in0, in1));
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return true;
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}
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/* Recognize patterns suitable for the ZIP instructions. */
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static bool
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aarch64_evpc_zip (struct expand_vec_perm_d *d)
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{
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unsigned int i, high, mask, nelt = d->nelt;
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rtx out, in0, in1, x;
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rtx (*gen) (rtx, rtx, rtx);
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enum machine_mode vmode = d->vmode;
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if (GET_MODE_UNIT_SIZE (vmode) > 8)
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return false;
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/* Note that these are little-endian tests.
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We correct for big-endian later. */
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high = nelt / 2;
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if (d->perm[0] == high)
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/* Do Nothing. */
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;
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else if (d->perm[0] == 0)
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high = 0;
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else
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return false;
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mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1);
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for (i = 0; i < nelt / 2; i++)
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{
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unsigned elt = (i + high) & mask;
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if (d->perm[i * 2] != elt)
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return false;
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elt = (elt + nelt) & mask;
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if (d->perm[i * 2 + 1] != elt)
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return false;
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}
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/* Success! */
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if (d->testing_p)
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return true;
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in0 = d->op0;
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in1 = d->op1;
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if (BYTES_BIG_ENDIAN)
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{
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x = in0, in0 = in1, in1 = x;
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high = !high;
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}
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out = d->target;
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if (high)
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_zip2v16qi; break;
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case V8QImode: gen = gen_aarch64_zip2v8qi; break;
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case V8HImode: gen = gen_aarch64_zip2v8hi; break;
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case V4HImode: gen = gen_aarch64_zip2v4hi; break;
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case V4SImode: gen = gen_aarch64_zip2v4si; break;
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case V2SImode: gen = gen_aarch64_zip2v2si; break;
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case V2DImode: gen = gen_aarch64_zip2v2di; break;
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case V4SFmode: gen = gen_aarch64_zip2v4sf; break;
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case V2SFmode: gen = gen_aarch64_zip2v2sf; break;
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case V2DFmode: gen = gen_aarch64_zip2v2df; break;
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default:
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return false;
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}
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}
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else
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{
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_zip1v16qi; break;
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case V8QImode: gen = gen_aarch64_zip1v8qi; break;
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case V8HImode: gen = gen_aarch64_zip1v8hi; break;
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case V4HImode: gen = gen_aarch64_zip1v4hi; break;
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case V4SImode: gen = gen_aarch64_zip1v4si; break;
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case V2SImode: gen = gen_aarch64_zip1v2si; break;
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case V2DImode: gen = gen_aarch64_zip1v2di; break;
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case V4SFmode: gen = gen_aarch64_zip1v4sf; break;
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case V2SFmode: gen = gen_aarch64_zip1v2sf; break;
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case V2DFmode: gen = gen_aarch64_zip1v2df; break;
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default:
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return false;
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}
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}
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emit_insn (gen (out, in0, in1));
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return true;
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}
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static bool
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aarch64_evpc_tbl (struct expand_vec_perm_d *d)
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{
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@ -6969,7 +7224,15 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
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}
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if (TARGET_SIMD)
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return aarch64_evpc_tbl (d);
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{
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if (aarch64_evpc_zip (d))
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return true;
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else if (aarch64_evpc_uzp (d))
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return true;
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else if (aarch64_evpc_trn (d))
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return true;
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return aarch64_evpc_tbl (d);
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}
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return false;
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}
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@ -230,6 +230,12 @@
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UNSPEC_BSL ; Used in aarch64-simd.md.
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UNSPEC_TBL ; Used in vector permute patterns.
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UNSPEC_CONCAT ; Used in vector permute patterns.
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UNSPEC_ZIP1 ; Used in vector permute patterns.
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UNSPEC_ZIP2 ; Used in vector permute patterns.
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UNSPEC_UZP1 ; Used in vector permute patterns.
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UNSPEC_UZP2 ; Used in vector permute patterns.
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UNSPEC_TRN1 ; Used in vector permute patterns.
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UNSPEC_TRN2 ; Used in vector permute patterns.
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])
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;; -------------------------------------------------------------------
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@ -652,6 +658,9 @@
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(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])
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(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
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UNSPEC_TRN1 UNSPEC_TRN2
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UNSPEC_UZP1 UNSPEC_UZP2])
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(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
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UNSPEC_FRINTI UNSPEC_FRINTX UNSPEC_FRINTA])
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@ -757,3 +766,10 @@
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(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
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(UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")])
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(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
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(UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
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(UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
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(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
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(UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
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(UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
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