i386.md (push mem DI peep2): New.
* i386.md (push mem DI peep2): New. (mov 0, mov -1 peep2): Handle 64bit. (lea to arithmetics peep2): Handle 64bit leas. (rsp arithmetics to push/pop peep2s): New. * i386.md (truncdfsf2_3, trunctfsf2_2): Change predicate to memory_operand. From-SVN: r40847
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
8362f4207e
commit
cc2e591b48
2 changed files with 183 additions and 7 deletions
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@ -1,3 +1,12 @@
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Mon Mar 26 15:55:08 CEST 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (push mem DI peep2): New.
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(mov 0, mov -1 peep2): Handle 64bit.
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(lea to arithmetics peep2): Handle 64bit leas.
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(rsp arithmetics to push/pop peep2s): New.
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* i386.md (truncdfsf2_3, trunctfsf2_2): Change predicate to memory_operand.
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Mon Mar 26 14:35:18 CEST 2001 Jan Hubicka <jh@suse.cz>
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* i386.c (struct machine_function): Add save_varrargs_registers.
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@ -4341,7 +4341,7 @@
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(set_attr "mode" "DF,SF")])
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(define_insn "truncdfsf2_3"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=m")
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[(set (match_operand:SF 0 "memory_operand" "=m")
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(float_truncate:SF
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(match_operand:DF 1 "register_operand" "f")))]
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"TARGET_80387"
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@ -4490,7 +4490,7 @@
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(set_attr "mode" "SF")])
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(define_insn "*trunctfsf2_2"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=m")
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[(set (match_operand:SF 0 "memory_operand" "=m")
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(float_truncate:SF
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(match_operand:TF 1 "register_operand" "f")))]
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"TARGET_80387"
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@ -15890,6 +15890,15 @@
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(set (match_dup 0) (match_dup 2))]
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"")
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(define_peephole2
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[(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "memory_operand" ""))
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(match_scratch:DI 2 "r")]
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"! optimize_size && ! TARGET_PUSH_MEMORY"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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;; We need to handle SFmode only, because DFmode and XFmode is split to
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;; SImode pushes.
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(define_peephole2
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@ -16209,12 +16218,14 @@
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(const_int 0))]
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"(GET_MODE (operands[0]) == QImode
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|| GET_MODE (operands[0]) == HImode
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|| GET_MODE (operands[0]) == SImode)
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|| GET_MODE (operands[0]) == SImode
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|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
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&& (! TARGET_USE_MOV0 || optimize_size)
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (const_int 0))
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(clobber (reg:CC 17))])]
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"operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
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"operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
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true_regnum (operands[0]));")
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(define_peephole2
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[(set (strict_low_part (match_operand 0 "register_operand" ""))
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@ -16231,12 +16242,14 @@
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[(set (match_operand 0 "register_operand" "")
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(const_int -1))]
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"(GET_MODE (operands[0]) == HImode
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|| GET_MODE (operands[0]) == SImode)
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|| GET_MODE (operands[0]) == SImode
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|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
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&& (optimize_size || TARGET_PENTIUM)
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (const_int -1))
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(clobber (reg:CC 17))])]
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"operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
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"operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
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true_regnum (operands[0]));")
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;; Attempt to convert simple leas to adds. These can be created by
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;; move expanders.
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@ -16249,16 +16262,55 @@
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(clobber (reg:CC 17))])]
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"")
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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(subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")) 0))]
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"peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
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[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC 17))])]
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"operands[2] = gen_lowpart (SImode, operands[2]);")
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand" "")
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(plus:DI (match_dup 0)
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(match_operand:DI 1 "x86_64_general_operand" "")))]
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"peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
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(clobber (reg:CC 17))])]
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"")
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (match_dup 0)
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(match_operand:SI 1 "immediate_operand" "")))]
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(match_operand:SI 1 "const_int_operand" "")))]
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"exact_log2 (INTVAL (operands[1])) >= 0
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC 17))])]
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
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(define_peephole2
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[(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (match_dup 0)
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(match_operand:DI 1 "const_int_operand" "")))]
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"exact_log2 (INTVAL (operands[1])) >= 0
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC 17))])]
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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(subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "const_int_operand" "")) 0))]
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"exact_log2 (INTVAL (operands[1])) >= 0
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&& REGNO (operands[0]) == REGNO (operands[1])
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC 17))])]
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"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
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;; The ESP adjustments can be done by the push and pop instructions. Resulting
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;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
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;; many CPUs it is also faster, since special hardware to avoid esp
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@ -16456,6 +16508,121 @@
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(clobber (match_dup 0))])]
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"")
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
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(set (reg:DI 6) (reg:DI 6))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_SUB_ESP_4"
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[(clobber (match_dup 0))
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(parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
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(set (reg:DI 6) (reg:DI 6))])])
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
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(set (reg:DI 6) (reg:DI 6))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_SUB_ESP_8"
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[(clobber (match_dup 0))
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(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
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(parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
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(set (reg:DI 6) (reg:DI 6))])])
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;; Convert esp substractions to push.
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_SUB_ESP_4"
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[(clobber (match_dup 0))
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(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_SUB_ESP_8"
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[(clobber (match_dup 0))
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(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
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(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
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;; Convert epilogue deallocator to pop.
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
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(set (reg:DI 6) (reg:DI 6))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_ADD_ESP_4"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
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(set (reg:DI 6) (reg:DI 6))])]
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"")
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;; Two pops case is tricky, since pop causes dependency on destination register.
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;; We use two registers if available.
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(match_scratch:DI 1 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
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(set (reg:DI 6) (reg:DI 6))
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(clobber (reg:CC 17))])]
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"optimize_size || !TARGET_ADD_ESP_8"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
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(set (reg:DI 6) (reg:DI 6))])
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(parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
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"")
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
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(set (reg:DI 6) (reg:DI 6))
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(clobber (reg:CC 17))])]
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"optimize_size"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
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(set (reg:DI 6) (reg:DI 6))])
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(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
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"")
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;; Convert esp additions to pop.
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
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(clobber (reg:CC 17))])]
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""
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
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"")
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;; Two pops case is tricky, since pop causes dependency on destination register.
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;; We use two registers if available.
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(match_scratch:DI 1 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
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(clobber (reg:CC 17))])]
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""
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
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(parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
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"")
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(define_peephole2
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[(match_scratch:DI 0 "r")
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(parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
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(clobber (reg:CC 17))])]
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"optimize_size"
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[(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
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(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
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(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
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"")
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;; Call-value patterns last so that the wildcard operand does not
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;; disrupt insn-recog's switch tables.
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