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RISC-V: Refine the condition for add additional vars in RVV cost model

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The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in smaller LMUL.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

	PR target/114506

gcc/ChangeLog:

	* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
	(need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.

Signed-off-by: demin.han <demin.han@starfivetech.com>
This commit is contained in:
demin.han 2024-03-26 16:52:12 +08:00
parent bca41a8d55
commit ca2f531cc5
2 changed files with 38 additions and 8 deletions
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23
gcc/config/riscv/riscv-vector-costs.cc
View file

@ -563,14 +563,24 @@ get_store_value (gimple *stmt)
return gimple_assign_rhs1 (stmt);
}
/* Return true if it is non-contiguous load/store. */
/* Return true if addtional vector vars needed. */
static bool
non_contiguous_memory_access_p (stmt_vec_info stmt_info)
need_additional_vector_vars_p (stmt_vec_info stmt_info)
{
enum stmt_vec_info_type type
= STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
return ((type == load_vec_info_type || type == store_vec_info_type)
&& !adjacent_dr_p (STMT_VINFO_DATA_REF (stmt_info)));
if (type == load_vec_info_type || type == store_vec_info_type)
{
if (STMT_VINFO_GATHER_SCATTER_P (stmt_info)
&& STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_GATHER_SCATTER)
return true;
machine_mode mode = TYPE_MODE (STMT_VINFO_VECTYPE (stmt_info));
int lmul = riscv_get_v_regno_alignment (mode);
if (DR_GROUP_SIZE (stmt_info) * lmul > RVV_M8)
return true;
}
return false;
}
/* Return the LMUL of the current analysis. */
@ -739,10 +749,7 @@ update_local_live_ranges (
stmt_vec_info stmt_info = vinfo->lookup_stmt (gsi_stmt (si));
enum stmt_vec_info_type type
= STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
if (non_contiguous_memory_access_p (stmt_info)
/* LOAD_LANES/STORE_LANES doesn't need a perm indice. */
&& STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info)
!= VMAT_LOAD_STORE_LANES)
if (need_additional_vector_vars_p (stmt_info))
{
/* For non-adjacent load/store STMT, we will potentially
convert it into:

23
gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c Normal file
View file

@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
float a[32000], b[32000], c[32000], d[32000];
float aa[256][256], bb[256][256], cc[256][256];
void
s2275 ()
{
for (int i = 0; i < 256; i++)
{
for (int j = 0; j < 256; j++)
{
aa[j][i] = aa[j][i] + bb[j][i] * cc[j][i];
}
a[i] = b[i] + c[i] * d[i];
}
}
/* { dg-final { scan-assembler-times {e32,m8} 1 } } */
/* { dg-final { scan-assembler-not {e32,m4} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */