i386.h (PRINT_OPERAND_PUNCT_VALID_P): Add ';' code.
* config/i386/i386.h (PRINT_OPERAND_PUNCT_VALID_P): Add ';' code. * config/i386/i386.c (print_operand): Handle ';' code. Output semicolon for TARGET_MACHO. * config/i386/sync.md (*sync_compare_and_swap<mode>): Use '%;' to emit semicolon after 'lock' prefix. (sync_double_compare_and_swap<mode>): Ditto. (*sync_double_compare_and_swapdi_pic): Ditto. (*sync_compare_and_swap_cc<mode>): Ditto. (sync_double_compare_and_swap_cc<mode>): Ditto. (*sync_double_compare_and_swap_ccdi_pic): Ditto. (sync_old_add<mode>): Ditto. (sync_add<mode>): Ditto. (sync_sub<mode>): Ditto. (sync_ior<mode>): Ditto. (sync_and<mode>): Ditto. (sync_xor<mode>): Ditto. From-SVN: r127728
This commit is contained in:
Uros Bizjak
parent
f4d8e0d1aa
commit
c9d259cb5e
4 changed files with 78 additions and 46 deletions
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@ -1,3 +1,22 @@
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2007-08-23 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (PRINT_OPERAND_PUNCT_VALID_P): Add ';' code.
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* config/i386/i386.c (print_operand): Handle ';' code. Output
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semicolon for TARGET_MACHO.
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* config/i386/sync.md (*sync_compare_and_swap<mode>): Use '%;' to
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emit semicolon after 'lock' prefix.
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(sync_double_compare_and_swap<mode>): Ditto.
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(*sync_double_compare_and_swapdi_pic): Ditto.
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(*sync_compare_and_swap_cc<mode>): Ditto.
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(sync_double_compare_and_swap_cc<mode>): Ditto.
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(*sync_double_compare_and_swap_ccdi_pic): Ditto.
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(sync_old_add<mode>): Ditto.
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(sync_add<mode>): Ditto.
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(sync_sub<mode>): Ditto.
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(sync_ior<mode>): Ditto.
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(sync_and<mode>): Ditto.
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(sync_xor<mode>): Ditto.
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2007-08-22 Chao-ying Fu <fu@mips.com>
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* rtl.c (rtx_code_size): Check CONST_FIXED to calcualte correct sizes
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@ -287,8 +306,8 @@
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* c-tree.h (enum c_typespec_keyword): Add cts_fract and cts_accum.
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(c_declspecs): Add saturating_p.
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* c-decl.c (build_null_declspecs): Initialize saturating_p.
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(declspecs_add_type): Avoid using complex with _Fract, _Accum, or _Sat.
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Handle RID_SAT.
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(declspecs_add_type): Avoid using complex with _Fract, _Accum, or
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_Sat. Handle RID_SAT.
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Avoid using void, bool, char, int, float, double, _Decimal32,
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_Decimal64, _Decimal128, and complex with _Sat.
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Handle RID_FRACT and RID_ACCUM.
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@ -584,14 +603,14 @@
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'nested_in_vect_loop' case. Change verbosity level.
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(vect_analyze_data_ref_access): Handle the 'nested_in_vect_loop' case.
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Don't fail on zero step in the outer-loop for loads.
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(vect_analyze_data_refs): Call split_constant_offset to calculate base,
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offset and init relative to the outer-loop.
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(vect_analyze_data_refs): Call split_constant_offset to calculate
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base, offset and init relative to the outer-loop.
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* tree-vect-transform.c (vect_create_data_ref_ptr): Replace the unused
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BSI function argument with a new function argument - at_loop.
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Simplify the condition that determines STEP. Takes additional argument
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INV_P. Support outer-loop vectorization (handle the nested_in_vect_loop
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case), including zero step in the outer-loop. Call
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INV_P. Support outer-loop vectorization (handle the
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nested_in_vect_loop case), including zero step in the outer-loop. Call
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vect_create_addr_base_for_vector_ref with additional argument.
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(vect_create_addr_base_for_vector_ref): Takes additional argument LOOP.
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Updated function documentation. Handle the 'nested_in_vect_loop' case.
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@ -601,12 +620,12 @@
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additional argument. Fix typos. Handle the 'nested_in_vect_loop' case.
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(vect_setup_realignment): Takes additional arguments INIT_ADDR and
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DR_ALIGNMENT_SUPPORT. Returns another value AT_LOOP. Handle the case
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when the realignment setup needs to take place inside the loop. Support
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the dr_explicit_realign scheme. Allow generating the optimized
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when the realignment setup needs to take place inside the loop.
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Support the dr_explicit_realign scheme. Allow generating the optimized
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realignment scheme for outer-loop vectorization. Added documentation.
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(vectorizable_load): Support the dr_explicit_realign scheme. Handle the
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'nested_in_vect_loop' case, including loads that are invariant in the
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outer-loop and the realignment schemes. Handle the case when the
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(vectorizable_load): Support the dr_explicit_realign scheme. Handle
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the 'nested_in_vect_loop' case, including loads that are invariant in
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the outer-loop and the realignment schemes. Handle the case when the
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realignment setup needs to take place inside the loop. Call
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vect_setup_realignment with additional arguments. Call
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vect_create_data_ref_ptr with additional argument and with loop instead
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@ -644,9 +663,9 @@
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(new_stmt_vec_info): When setting def_type for phis differentiate
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loop-header phis from other phis.
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(bb_in_loop_p): New function.
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(new_loop_vec_info): Inner-loop phis already have a stmt_vinfo, so just
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update their loop_vinfo. Order of BB traversal now matters - call
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dfs_enumerate_from with bb_in_loop_p.
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(new_loop_vec_info): Inner-loop phis already have a stmt_vinfo, so
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just update their loop_vinfo. Order of BB traversal now matters -
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call dfs_enumerate_from with bb_in_loop_p.
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(destroy_loop_vec_info): Takes additional argument to control whether
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stmt_vinfo of the loop stmts should be destroyed as well.
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(vect_is_simple_reduction): Allow the "non-reduction" use of a
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@ -1105,8 +1124,8 @@
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(add_back_forw_dep, delete_back_forw_dep): Ditto.
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(debug_ds, sched_insn_is_legitimate_for_speculation_p): Declare
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functions.
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(SD_LIST_NONE, SD_LIST_HARD_BACK, SD_LIST_SPEC_BACK, SD_LIST_FORW): New
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constants.
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(SD_LIST_NONE, SD_LIST_HARD_BACK, SD_LIST_SPEC_BACK, SD_LIST_FORW):
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New constants.
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(SD_LIST_RES_BACK, SD_LIST_RES_FORW, SD_LIST_BACK): Ditto.
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(sd_list_types_def): New typedef.
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(sd_next_list): Declare function.
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@ -1247,8 +1266,8 @@
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Free dependencies at the end of scheduling the ebb.
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* ddg.c (create_ddg_dependence): Update to use new interfaces.
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(build_intra_loop_deps): Ditto. Remove separate computation of forward
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dependencies. Free sched-deps dependencies.
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(build_intra_loop_deps): Ditto. Remove separate computation of
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forward dependencies. Free sched-deps dependencies.
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* config/ia64/ia64.c (ia64_dependencies_evaluation_hook): Update
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to use new interfaces.
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@ -2322,13 +2341,14 @@
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2007-08-04 Andrew Pinski <andrew_pinski@playstation.sony.com>
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PR middle-end/32780
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* fold-const.c (fold_binary <case MINUS_EXPR>): Fix the type of operands
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for the folding of "A - (A & B)" into "~B & A"; cast them to type.
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* fold-const.c (fold_binary <case MINUS_EXPR>): Fix the type of
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operands for the folding of "A - (A & B)" into "~B & A"; cast them
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to type.
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2007-08-03 Zdenek Dvorak <ook@ucw.cz>
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* tree-ssa-threadupdate.c (thread_through_all_blocks): Use loops' state
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accessor functions.
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* tree-ssa-threadupdate.c (thread_through_all_blocks): Use loops'
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state accessor functions.
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* cfgloopmanip.c (remove_path, create_preheaders,
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force_single_succ_latches, fix_loop_structure): Ditto.
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* tree-ssa-loop-manip.c (rewrite_into_loop_closed_ssa,
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@ -3211,8 +3231,8 @@
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2007-07-27 Jan Hubicka <jh@suse.cz>
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* config/i386/i386.c (register_move_cost): Remove accidentally comitted
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#if 0 block.
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* config/i386/i386.c (register_move_cost): Remove accidentally
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comitted #if 0 block.
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* attribs.c: Include hashtab.h
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(attribute_hash): New.
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@ -4141,7 +4161,8 @@
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Jakub Jelinek <jakub@redhat.com>
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PR middle-end/PR28690
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* optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow EQ compares.
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* optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow
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EQ compares.
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* rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
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and MEM_POINTER operands over REG and MEM operands.
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(swap_commutative_operands_p): Change return value to bool.
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@ -4187,8 +4208,8 @@
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(expand_copysign_absneg): If back end provides signbit insn, use it
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instead of bit operations on floating point argument.
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* builtins.c (enum insn_code signbit_optab[]): Remove array.
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(expand_builtin_signbit): Check signbit_optab->handlers[].insn_code for
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availability of signbit insn.
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(expand_builtin_signbit): Check signbit_optab->handlers[].insn_code
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for availability of signbit insn.
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* config/i386/i386.md (signbit<mode>2): New insn pattern to implement
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signbitf, signbit and signbitl built-ins as inline x87 intrinsics when
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@ -4473,8 +4494,8 @@
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* pa-protos.h (pa_eh_return_handler_rtx): Declare.
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* pa.c (pa_extra_live_on_entry, rp_saved): Declare.
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(TARGET_EXTRA_LIVE_ON_ENTRY): Define.
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(pa_output_function_prologue): Use rp_saved and current_function_is_leaf
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to generate .CALLINFO statement.
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(pa_output_function_prologue): Use rp_saved and
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current_function_is_leaf to generate .CALLINFO statement.
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(hppa_expand_prologue): Set rp_saved.
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(hppa_expand_epilogue): Use rp_saved.
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(pa_extra_live_on_entry, pa_eh_return_handler_rtx): New functions.
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@ -8495,6 +8495,8 @@ get_some_local_dynamic_name (void)
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X -- don't print any sort of PIC '@' suffix for a symbol.
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& -- print some in-use local-dynamic symbol name.
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H -- print a memory address offset by 8; used for sse high-parts
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+ -- print a branch hint as 'cs' or 'ds' prefix
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; -- print a semicolon (after prefixes due to bug in older gas).
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*/
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void
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@ -8776,6 +8778,15 @@ print_operand (FILE *file, rtx x, int code)
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}
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return;
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}
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case ';':
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#if TARGET_MACHO
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fputs (" ; ", file);
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#else
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fputc (' ', file);
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#endif
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return;
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default:
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output_operand_lossage ("invalid operand code '%c'", code);
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}
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@ -2229,7 +2229,7 @@ do { \
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print_operand function. */
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#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
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((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
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((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
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#define PRINT_OPERAND(FILE, X, CODE) \
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print_operand ((FILE), (X), (CODE))
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@ -81,7 +81,7 @@
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_CMPXCHG"
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"lock cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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"lock{%;| } cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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(define_insn "sync_double_compare_and_swap<mode>"
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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@ -95,7 +95,7 @@
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock cmpxchg<doublemodesuffix>b\t%1")
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"lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
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;; Theoretically we'd like to use constraint "r" (any reg) for operand
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;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
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@ -118,7 +118,7 @@
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"xchg{l}\t%%ebx, %3\;lock cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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"xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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(define_expand "sync_compare_and_swap_cc<mode>"
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[(parallel
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@ -176,7 +176,7 @@
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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"TARGET_CMPXCHG"
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"lock cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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"lock{%;| }cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
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(define_insn "sync_double_compare_and_swap_cc<mode>"
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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@ -195,7 +195,7 @@
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UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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""
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"lock cmpxchg<doublemodesuffix>b\t%1")
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"lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
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;; See above for the explanation of using the constraint "SD" for
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;; operand 3.
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@ -216,7 +216,7 @@
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UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"xchg{l}\t%%ebx, %3\;lock cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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"xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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(define_insn "sync_old_add<mode>"
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[(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
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@ -227,7 +227,7 @@
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(match_operand:IMODE 2 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_XADD"
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"lock xadd{<modesuffix>}\t{%0, %1|%1, %0}")
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"lock{%;| }xadd{<modesuffix>}\t{%0, %1|%1, %0}")
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;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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(define_insn "sync_lock_test_and_set<mode>"
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@ -251,12 +251,12 @@
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if (TARGET_USE_INCDEC)
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{
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if (operands[1] == const1_rtx)
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return "lock inc{<modesuffix>}\t%0";
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return "lock{%;| }inc{<modesuffix>}\t%0";
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if (operands[1] == constm1_rtx)
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return "lock dec{<modesuffix>}\t%0";
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return "lock{%;| }dec{<modesuffix>}\t%0";
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}
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return "lock add{<modesuffix>}\t{%1, %0|%0, %1}";
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return "lock{%;| }add{<modesuffix>}\t{%1, %0|%0, %1}";
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})
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(define_insn "sync_sub<mode>"
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@ -271,12 +271,12 @@
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if (TARGET_USE_INCDEC)
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{
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if (operands[1] == const1_rtx)
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return "lock dec{<modesuffix>}\t%0";
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return "lock{%;| }dec{<modesuffix>}\t%0";
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if (operands[1] == constm1_rtx)
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return "lock inc{<modesuffix>}\t%0";
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return "lock{%;| }inc{<modesuffix>}\t%0";
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}
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return "lock sub{<modesuffix>}\t{%1, %0|%0, %1}";
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return "lock{%;| }sub{<modesuffix>}\t{%1, %0|%0, %1}";
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})
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(define_insn "sync_ior<mode>"
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@ -287,7 +287,7 @@
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock or{<modesuffix>}\t{%1, %0|%0, %1}")
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"lock{%;| }or{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_and<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "+m")
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@ -297,7 +297,7 @@
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock and{<modesuffix>}\t{%1, %0|%0, %1}")
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"lock{%;| }and{<modesuffix>}\t{%1, %0|%0, %1}")
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(define_insn "sync_xor<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "+m")
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@ -307,4 +307,4 @@
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UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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""
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"lock xor{<modesuffix>}\t{%1, %0|%0, %1}")
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"lock{%;| }xor{<modesuffix>}\t{%1, %0|%0, %1}")
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