diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 87af8f3689c..01cd85d64fd 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -263,16 +263,14 @@ BUILTIN_VQN (SHIFTIMM, shrn_n, 0, NONE) BUILTIN_VQN (USHIFTIMM, shrn_n, 0, NONE) - /* Implemented by aarch64_shrn2. */ - BUILTIN_VQN (SHIFT2IMM, shrn2, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, shrn2, 0, NONE) + BUILTIN_VQN (SHIFT2IMM, shrn2_n, 0, NONE) + BUILTIN_VQN (USHIFT2IMM, shrn2_n, 0, NONE) BUILTIN_VQN (SHIFTIMM, rshrn_n, 0, NONE) BUILTIN_VQN (USHIFTIMM, rshrn_n, 0, NONE) - /* Implemented by aarch64_rshrn2. */ - BUILTIN_VQN (SHIFT2IMM, rshrn2, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, rshrn2, 0, NONE) + BUILTIN_VQN (SHIFT2IMM, rshrn2_n, 0, NONE) + BUILTIN_VQN (USHIFT2IMM, rshrn2_n, 0, NONE) /* Implemented by aarch64_mlsl. */ BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) @@ -480,7 +478,6 @@ BUILTIN_SD_HSDI (USHIFTIMM, uqshrn_n, 0, NONE) BUILTIN_SD_HSDI (SHIFTIMM, sqrshrn_n, 0, NONE) BUILTIN_SD_HSDI (USHIFTIMM, uqrshrn_n, 0, NONE) - /* Implemented by aarch64_qshrn2_n. */ BUILTIN_VQN (SHIFT2IMM_UUSS, sqshrun2_n, 0, NONE) BUILTIN_VQN (SHIFT2IMM_UUSS, sqrshrun2_n, 0, NONE) BUILTIN_VQN (SHIFT2IMM, sqshrn2_n, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index ce5885e7bb1..b31c7130708 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1896,30 +1896,6 @@ } ) -(define_insn "*aarch64_shrn2_vect_le" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (match_operand: 1 "register_operand" "0") - (truncate: - (SHIFTRT:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "shrn2\\t%0., %2., %3" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_insn "*aarch64_shrn2_vect_be" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (truncate: - (SHIFTRT:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_"))) - (match_operand: 1 "register_operand" "0")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "shrn2\\t%0., %2., %3" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - (define_insn "*aarch64_topbits_shuffle_le" [(set (match_operand: 0 "register_operand" "=w") (vec_concat: @@ -1948,121 +1924,6 @@ [(set_attr "type" "neon_permute")] ) -(define_insn "aarch64_shrn2_insn_le" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (match_operand: 1 "register_operand" "0") - (truncate: - (lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "shrn2\\t%0., %2., %3" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_insn "aarch64_shrn2_insn_be" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (truncate: - (lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 - "aarch64_simd_shift_imm_vec_"))) - (match_operand: 1 "register_operand" "0")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "shrn2\\t%0., %2., %3" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_expand "aarch64_shrn2" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQN 2 "register_operand") - (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] - "TARGET_SIMD" - { - operands[3] = aarch64_simd_gen_const_vector_dup (mode, - INTVAL (operands[3])); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_shrn2_insn_be (operands[0], operands[1], - operands[2], operands[3])); - else - emit_insn (gen_aarch64_shrn2_insn_le (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } -) - -(define_insn "aarch64_rshrn2_insn_le" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (match_operand: 1 "register_operand" "0") - (truncate: - (lshiftrt:VQN - (plus:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 "aarch64_simd_rshrn_imm_vec")) - (match_operand:VQN 4 "aarch64_simd_shift_imm_vec_")))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN - && INTVAL (CONST_VECTOR_ELT (operands[3], 0)) - == (HOST_WIDE_INT_1 << (INTVAL (CONST_VECTOR_ELT (operands[4], 0)) - 1))" - "rshrn2\\t%0., %2., %4" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_insn "aarch64_rshrn2_insn_be" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (truncate: - (lshiftrt:VQN - (plus:VQN (match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 "aarch64_simd_rshrn_imm_vec")) - (match_operand:VQN 4 "aarch64_simd_shift_imm_vec_"))) - (match_operand: 1 "register_operand" "0")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN - && INTVAL (CONST_VECTOR_ELT (operands[3], 0)) - == (HOST_WIDE_INT_1 << (INTVAL (CONST_VECTOR_ELT (operands[4], 0)) - 1))" - "rshrn2\\t%0., %2., %4" - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_expand "aarch64_rshrn2" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand:VQN 2 "register_operand") - (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] - "TARGET_SIMD" - { - if (INTVAL (operands[3]) == GET_MODE_UNIT_BITSIZE (mode)) - { - rtx tmp = aarch64_gen_shareable_zero (mode); - emit_insn (gen_aarch64_raddhn2 (operands[0], operands[1], - operands[2], tmp)); - } - else - { - rtx shft - = aarch64_simd_gen_const_vector_dup (mode, - HOST_WIDE_INT_1U - << (INTVAL (operands[3]) - 1)); - - operands[3] = aarch64_simd_gen_const_vector_dup (mode, - INTVAL (operands[3])); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_rshrn2_insn_be (operands[0], - operands[1], - operands[2], - shft, - operands[3])); - else - emit_insn (gen_aarch64_rshrn2_insn_le (operands[0], - operands[1], - operands[2], - shft, - operands[3])); - } - DONE; - } -) - ;; Widening operations. (define_insn "aarch64_simd_vec_unpack_lo_" @@ -6912,54 +6773,254 @@ } ) -(define_insn "aarch64_qshrn2_n_insn_le" +(define_insn "aarch64_shrn2_n_insn_le" [(set (match_operand: 0 "register_operand" "=w") (vec_concat: (match_operand: 1 "register_operand" "0") - (unspec: [(match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 - "aarch64_simd_shift_imm_vec_")] - VQSHRN_N)))] + (ALL_TRUNC: + (:VQN + (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")))))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "qshrn2\\t%0., %2., %3" - [(set_attr "type" "neon_sat_shift_imm_narrow_q")] + "shrn2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] ) -(define_insn "aarch64_qshrn2_n_insn_be" +(define_insn "aarch64_shrn2_n_insn_be" [(set (match_operand: 0 "register_operand" "=w") (vec_concat: - (unspec: [(match_operand:VQN 2 "register_operand" "w") - (match_operand:VQN 3 - "aarch64_simd_shift_imm_vec_")] - VQSHRN_N) + (ALL_TRUNC: + (:VQN + (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_"))) (match_operand: 1 "register_operand" "0")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" - "qshrn2\\t%0., %2., %3" - [(set_attr "type" "neon_sat_shift_imm_narrow_q")] + "shrn2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] ) -(define_expand "aarch64_qshrn2_n" +(define_expand "aarch64_shrn2_n" [(match_operand: 0 "register_operand") (match_operand: 1 "register_operand") - (unspec: - [(match_operand:VQN 2 "register_operand") - (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] - VQSHRN_N)] + (ALL_TRUNC: + (match_operand:VQN 2 "register_operand")) + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] "TARGET_SIMD" { operands[3] = aarch64_simd_gen_const_vector_dup (mode, INTVAL (operands[3])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_qshrn2_n_insn_be (operands[0], + emit_insn (gen_aarch64_shrn2_n_insn_be (operands[0], operands[1], operands[2], operands[3])); else - emit_insn (gen_aarch64_qshrn2_n_insn_le (operands[0], + emit_insn (gen_aarch64_shrn2_n_insn_le (operands[0], operands[1], operands[2], operands[3])); DONE; } ) +(define_insn "aarch64_rshrn2_n_insn_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 1 "register_operand" "0") + (ALL_TRUNC: + (: + (plus: + (: + (match_operand:VQN 2 "register_operand" "w")) + (match_operand: 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN + && aarch64_const_vec_rnd_cst_p (operands[4], operands[3])" + "rshrn2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_rshrn2_n_insn_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (ALL_TRUNC: + (: + (plus: + (: + (match_operand:VQN 2 "register_operand" "w")) + (match_operand: 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_"))) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN + && aarch64_const_vec_rnd_cst_p (operands[4], operands[3])" + "rshrn2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_rshrn2_n" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (ALL_TRUNC: (match_operand:VQN 2 "register_operand")) + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] + "TARGET_SIMD" + { + if ( == TRUNCATE + && INTVAL (operands[3]) == GET_MODE_UNIT_BITSIZE (mode)) + { + rtx tmp = aarch64_gen_shareable_zero (mode); + emit_insn (gen_aarch64_raddhn2 (operands[0], operands[1], + operands[2], tmp)); + DONE; + } + /* Use this expander to create the rounding constant vector, which is + 1 << (shift - 1). Use wide_int here to ensure that the right TImode + RTL is generated when handling the DImode expanders. */ + int prec = GET_MODE_UNIT_PRECISION (mode); + wide_int rnd_wi = wi::set_bit_in_zero (INTVAL (operands[3]) - 1, prec); + rtx rnd = immed_wide_int_const (rnd_wi, GET_MODE_INNER (mode)); + rnd = gen_const_vec_duplicate (mode, rnd); + operands[3] = gen_const_vec_duplicate (mode, operands[3]); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_rshrn2_n_insn_be (operands[0], + operands[1], + operands[2], + operands[3], + rnd)); + else + emit_insn (gen_aarch64_rshrn2_n_insn_le (operands[0], + operands[1], + operands[2], + operands[3], + rnd)); + DONE; + } +) + +(define_insn "aarch64_sqshrun2_n_insn_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 1 "register_operand" "0") + (truncate: + (smin:VQN + (smax:VQN + (ashiftrt:VQN + (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")) + (match_operand:VQN 4 "aarch64_simd_imm_zero")) + (match_operand:VQN 5 "aarch64_simd_umax_half_mode")))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "sqshrun2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_sqshrun2_n_insn_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (truncate: + (smin:VQN + (smax:VQN + (ashiftrt:VQN + (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")) + (match_operand:VQN 4 "aarch64_simd_imm_zero")) + (match_operand:VQN 5 "aarch64_simd_umax_half_mode"))) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "sqshrun2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_sqshrun2_n" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (match_operand:VQN 2 "register_operand") + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] + "TARGET_SIMD" + { + operands[3] = aarch64_simd_gen_const_vector_dup (mode, + INTVAL (operands[3])); + rtx zeros = CONST0_RTX (mode); + rtx half_umax + = aarch64_simd_gen_const_vector_dup (mode, + GET_MODE_MASK (GET_MODE_INNER (mode))); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_sqshrun2_n_insn_be (operands[0], + operands[1], operands[2], operands[3], + zeros, half_umax)); + else + emit_insn (gen_aarch64_sqshrun2_n_insn_le (operands[0], + operands[1], operands[2], operands[3], + zeros, half_umax)); + DONE; + } +) + +(define_insn "aarch64_sqrshrun2_n_insn_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 1 "register_operand" "0") + (truncate: + (smin: + (smax: + (ashiftrt: + (plus: + (sign_extend: + (match_operand:VQN 2 "register_operand" "w")) + (match_operand: 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")) + (match_operand: 5 "aarch64_simd_imm_zero")) + (match_operand: 6 "aarch64_simd_umax_quarter_mode")))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN + && aarch64_const_vec_rnd_cst_p (operands[4], operands[3])" + "sqrshrun2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_sqrshrun2_n_insn_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (truncate: + (smin: + (smax: + (ashiftrt: + (plus: + (sign_extend: + (match_operand:VQN 2 "register_operand" "w")) + (match_operand: 4 "aarch64_simd_rsra_rnd_imm_vec")) + (match_operand:VQN 3 "aarch64_simd_shift_imm_vec_")) + (match_operand: 5 "aarch64_simd_imm_zero")) + (match_operand: 6 "aarch64_simd_umax_quarter_mode"))) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN + && aarch64_const_vec_rnd_cst_p (operands[4], operands[3])" + "sqrshrun2\t%0., %2., %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_sqrshrun2_n" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (match_operand:VQN 2 "register_operand") + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_")] + "TARGET_SIMD" + { + int prec = GET_MODE_UNIT_PRECISION (mode); + wide_int rnd_wi = wi::set_bit_in_zero (INTVAL (operands[3]) - 1, prec); + rtx rnd = immed_wide_int_const (rnd_wi, GET_MODE_INNER (mode)); + rnd = gen_const_vec_duplicate (mode, rnd); + rtx zero = CONST0_RTX (mode); + rtx half_umax + = aarch64_simd_gen_const_vector_dup (mode, + GET_MODE_MASK (GET_MODE_INNER (mode))); + operands[3] = gen_const_vec_duplicate (mode, operands[3]); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_sqrshrun2_n_insn_be (operands[0], + operands[1], operands[2], operands[3], rnd, + zero, half_umax)); + else + emit_insn (gen_aarch64_sqrshrun2_n_insn_le (operands[0], + operands[1], operands[2], operands[3], rnd, + zero, half_umax)); + DONE; + } +) ;; cm(eq|ge|gt|lt|le) ;; Note, we have constraints for Dz and Z as different expanders diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 2a46a31b617..d350d9e7c01 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5532,42 +5532,42 @@ __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_s16 (int8x8_t __a, int16x8_t __b, const int __c) { - return __builtin_aarch64_rshrn2v8hi (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv8hi (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_s32 (int16x4_t __a, int32x4_t __b, const int __c) { - return __builtin_aarch64_rshrn2v4si (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv4si (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_s64 (int32x2_t __a, int64x2_t __b, const int __c) { - return __builtin_aarch64_rshrn2v2di (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv2di (__a, __b, __c); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c) { - return __builtin_aarch64_rshrn2v8hi_uuus (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv8hi_uuus (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c) { - return __builtin_aarch64_rshrn2v4si_uuus (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv4si_uuus (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c) { - return __builtin_aarch64_rshrn2v2di_uuus (__a, __b, __c); + return __builtin_aarch64_rshrn2_nv2di_uuus (__a, __b, __c); } __extension__ extern __inline int8x8_t @@ -5630,42 +5630,42 @@ __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_s16 (int8x8_t __a, int16x8_t __b, const int __c) { - return __builtin_aarch64_shrn2v8hi (__a, __b, __c); + return __builtin_aarch64_shrn2_nv8hi (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_s32 (int16x4_t __a, int32x4_t __b, const int __c) { - return __builtin_aarch64_shrn2v4si (__a, __b, __c); + return __builtin_aarch64_shrn2_nv4si (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_s64 (int32x2_t __a, int64x2_t __b, const int __c) { - return __builtin_aarch64_shrn2v2di (__a, __b, __c); + return __builtin_aarch64_shrn2_nv2di (__a, __b, __c); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c) { - return __builtin_aarch64_shrn2v8hi_uuus (__a, __b, __c); + return __builtin_aarch64_shrn2_nv8hi_uuus (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c) { - return __builtin_aarch64_shrn2v4si_uuus (__a, __b, __c); + return __builtin_aarch64_shrn2_nv4si_uuus (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c) { - return __builtin_aarch64_shrn2v2di_uuus (__a, __b, __c); + return __builtin_aarch64_shrn2_nv2di_uuus (__a, __b, __c); } __extension__ extern __inline poly8x8_t diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 15436c8ef37..7f9a512809d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -645,12 +645,6 @@ UNSPEC_SQSHLU ; Used in aarch64-simd.md. UNSPEC_SQSHL ; Used in aarch64-simd.md. UNSPEC_UQSHL ; Used in aarch64-simd.md. - UNSPEC_SQSHRUN ; Used in aarch64-simd.md. - UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. - UNSPEC_SQSHRN ; Used in aarch64-simd.md. - UNSPEC_UQSHRN ; Used in aarch64-simd.md. - UNSPEC_SQRSHRN ; Used in aarch64-simd.md. - UNSPEC_UQRSHRN ; Used in aarch64-simd.md. UNSPEC_SSHL ; Used in aarch64-simd.md. UNSPEC_USHL ; Used in aarch64-simd.md. UNSPEC_SRSHL ; Used in aarch64-simd.md. @@ -2660,10 +2654,6 @@ (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) -(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN - UNSPEC_SQSHRN UNSPEC_UQSHRN - UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) - (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 @@ -3374,9 +3364,6 @@ (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") (UNSPEC_UQSHL "u") - (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") - (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") - (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") (UNSPEC_USHL "u") (UNSPEC_SSHL "s") (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") @@ -3388,9 +3375,6 @@ ]) (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") - (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") - (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") - (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") (UNSPEC_SMULHS "") (UNSPEC_UMULHS "") @@ -3406,9 +3390,6 @@ (UNSPEC_SLI "l") (UNSPEC_SRI "r")]) (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") - (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") - (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") - (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "") (UNSPEC_SHADD "") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])