x86-tune-costs.h (bdver?_memcpy, [...]): Unify to ...
2018-10-11 Richard Biener <rguenther@suse.de> * config/i386/x86-tune-costs.h (bdver?_memcpy, bdver?_memset, bdver?_cost): Unify to ... (bdver_memcpy, bdver_memset, bdver_cost): ... this. * config/i386/i386.c (processor_cost_table): Adjust. From-SVN: r265038
This commit is contained in:
Richard Biener
Richard Biener
parent
c1b48b2929
commit
c727b83513
3 changed files with 17 additions and 316 deletions
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@ -1,3 +1,10 @@
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2018-10-11 Richard Biener <rguenther@suse.de>
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* config/i386/x86-tune-costs.h (bdver?_memcpy, bdver?_memset,
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bdver?_cost): Unify to ...
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(bdver_memcpy, bdver_memset, bdver_cost): ... this.
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* config/i386/i386.c (processor_cost_table): Adjust.
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2018-10-10 Eric Botcazou <ebotcazou@adacore.com>
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PR middle-end/87574
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@ -861,10 +861,10 @@ static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
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&athlon_cost,
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&k8_cost,
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&amdfam10_cost,
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&bdver1_cost,
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&bdver2_cost,
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&bdver3_cost,
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&bdver4_cost,
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&bdver_cost,
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&bdver_cost,
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&bdver_cost,
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&bdver_cost,
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&btver1_cost,
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&btver2_cost,
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&znver1_cost,
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@ -1047,21 +1047,21 @@ struct processor_costs amdfam10_cost = {
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"32", /* Func alignment. */
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};
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/* BDVER1 has optimized REP instruction for medium sized blocks, but for
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/* BDVER has optimized REP instruction for medium sized blocks, but for
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very small blocks it is better to use loop. For large blocks, libcall
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can do nontemporary accesses and beat inline considerably. */
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static stringop_algs bdver1_memcpy[2] = {
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static stringop_algs bdver_memcpy[2] = {
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{libcall, {{6, loop, false}, {14, unrolled_loop, false},
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{-1, rep_prefix_4_byte, false}}},
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{libcall, {{16, loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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static stringop_algs bdver1_memset[2] = {
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static stringop_algs bdver_memset[2] = {
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{libcall, {{8, loop, false}, {24, unrolled_loop, false},
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{2048, rep_prefix_4_byte, false}, {-1, libcall, false}}},
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{libcall, {{48, unrolled_loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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const struct processor_costs bdver1_cost = {
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const struct processor_costs bdver_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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@ -1139,314 +1139,8 @@ const struct processor_costs bdver1_cost = {
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COSTS_N_INSNS (15), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (26), /* cost of SQRTSD instruction. */
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1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
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bdver1_memcpy,
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bdver1_memset,
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COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
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COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
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"16:11:8", /* Loop alignment. */
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"16:8:8", /* Jump alignment. */
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"0:0:8", /* Label alignment. */
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"11", /* Func alignment. */
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};
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/* BDVER2 has optimized REP instruction for medium sized blocks, but for
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very small blocks it is better to use loop. For large blocks, libcall
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can do nontemporary accesses and beat inline considerably. */
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static stringop_algs bdver2_memcpy[2] = {
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{libcall, {{6, loop, false}, {14, unrolled_loop, false},
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{-1, rep_prefix_4_byte, false}}},
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{libcall, {{16, loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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static stringop_algs bdver2_memset[2] = {
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{libcall, {{8, loop, false}, {24, unrolled_loop, false},
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{2048, rep_prefix_4_byte, false}, {-1, libcall, false}}},
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{libcall, {{48, unrolled_loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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const struct processor_costs bdver2_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (4), /* cost of starting multiply for QI */
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COSTS_N_INSNS (4), /* HI */
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COSTS_N_INSNS (4), /* SI */
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COSTS_N_INSNS (6), /* DI */
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COSTS_N_INSNS (6)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (35), /* HI */
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COSTS_N_INSNS (51), /* SI */
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COSTS_N_INSNS (83), /* DI */
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COSTS_N_INSNS (83)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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9, /* MOVE_RATIO */
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/* All move costs are relative to integer->integer move times 2 and thus
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they are latency*2. */
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8, /* cost for loading QImode using movzbl */
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{8, 8, 8}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer registers */
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4, /* cost of reg,reg fld/fst */
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{12, 12, 28}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{10, 10, 18}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode */
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4, /* cost of moving MMX register */
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{12, 12}, /* cost of loading MMX registers
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in SImode and DImode */
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{10, 10}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{12, 12, 10, 20, 30}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{12, 12, 10, 20, 30}, /* cost of unaligned loads. */
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{10, 10, 10, 20, 30}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 10, 20, 30}, /* cost of unaligned stores. */
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16, 20, /* SSE->integer and integer->SSE moves */
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12, 12, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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16, /* size of l1 cache. */
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2048, /* size of l2 cache. */
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64, /* size of prefetch block */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
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time). */
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100, /* number of parallel prefetches */
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2, /* Branch cost */
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COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (6), /* cost of FMUL instruction. */
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COSTS_N_INSNS (42), /* cost of FDIV instruction. */
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COSTS_N_INSNS (2), /* cost of FABS instruction. */
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COSTS_N_INSNS (2), /* cost of FCHS instruction. */
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COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (2), /* cost of cheap SSE instruction. */
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COSTS_N_INSNS (6), /* cost of ADDSS/SD SUBSS/SD insns. */
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COSTS_N_INSNS (6), /* cost of MULSS instruction. */
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COSTS_N_INSNS (6), /* cost of MULSD instruction. */
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COSTS_N_INSNS (6), /* cost of FMA SS instruction. */
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COSTS_N_INSNS (6), /* cost of FMA SD instruction. */
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/* 9-24 */
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COSTS_N_INSNS (24), /* cost of DIVSS instruction. */
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/* 9-27 */
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COSTS_N_INSNS (27), /* cost of DIVSD instruction. */
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COSTS_N_INSNS (15), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (26), /* cost of SQRTSD instruction. */
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1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
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bdver2_memcpy,
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bdver2_memset,
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COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
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COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
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"16:11:8", /* Loop alignment. */
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"16:8:8", /* Jump alignment. */
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"0:0:8", /* Label alignment. */
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"11", /* Func alignment. */
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};
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/* BDVER3 has optimized REP instruction for medium sized blocks, but for
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very small blocks it is better to use loop. For large blocks, libcall
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can do nontemporary accesses and beat inline considerably. */
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static stringop_algs bdver3_memcpy[2] = {
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{libcall, {{6, loop, false}, {14, unrolled_loop, false},
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{-1, rep_prefix_4_byte, false}}},
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{libcall, {{16, loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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static stringop_algs bdver3_memset[2] = {
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{libcall, {{8, loop, false}, {24, unrolled_loop, false},
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{2048, rep_prefix_4_byte, false}, {-1, libcall, false}}},
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{libcall, {{48, unrolled_loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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struct processor_costs bdver3_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (4), /* cost of starting multiply for QI */
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COSTS_N_INSNS (4), /* HI */
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COSTS_N_INSNS (4), /* SI */
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COSTS_N_INSNS (6), /* DI */
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COSTS_N_INSNS (6)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (35), /* HI */
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COSTS_N_INSNS (51), /* SI */
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COSTS_N_INSNS (83), /* DI */
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COSTS_N_INSNS (83)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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9, /* MOVE_RATIO */
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/* All move costs are relative to integer->integer move times 2 and thus
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they are latency*2. */
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8, /* cost for loading QImode using movzbl */
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{8, 8, 8}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer registers */
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4, /* cost of reg,reg fld/fst */
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{12, 12, 28}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{10, 10, 18}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode */
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4, /* cost of moving MMX register */
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{12, 12}, /* cost of loading MMX registers
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in SImode and DImode */
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{10, 10}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{12, 12, 10, 20, 30}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{12, 12, 10, 20, 30}, /* cost of unaligned loads. */
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{10, 10, 10, 20, 30}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 10, 20, 30}, /* cost of unaligned stores. */
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16, 20, /* SSE->integer and integer->SSE moves */
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12, 12, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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16, /* size of l1 cache. */
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2048, /* size of l2 cache. */
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64, /* size of prefetch block */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
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time). */
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100, /* number of parallel prefetches */
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2, /* Branch cost */
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COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (6), /* cost of FMUL instruction. */
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COSTS_N_INSNS (42), /* cost of FDIV instruction. */
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COSTS_N_INSNS (2), /* cost of FABS instruction. */
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COSTS_N_INSNS (2), /* cost of FCHS instruction. */
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COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (2), /* cost of cheap SSE instruction. */
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COSTS_N_INSNS (6), /* cost of ADDSS/SD SUBSS/SD insns. */
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COSTS_N_INSNS (6), /* cost of MULSS instruction. */
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COSTS_N_INSNS (6), /* cost of MULSD instruction. */
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COSTS_N_INSNS (6), /* cost of FMA SS instruction. */
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COSTS_N_INSNS (6), /* cost of FMA SD instruction. */
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/* 9-24 */
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COSTS_N_INSNS (24), /* cost of DIVSS instruction. */
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/* 9-27 */
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COSTS_N_INSNS (27), /* cost of DIVSD instruction. */
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COSTS_N_INSNS (15), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (26), /* cost of SQRTSD instruction. */
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1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
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bdver3_memcpy,
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bdver3_memset,
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COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
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COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
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"16:11:8", /* Loop alignment. */
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"16:8:8", /* Jump alignment. */
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"0:0:8", /* Label alignment. */
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"11", /* Func alignment. */
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};
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/* BDVER4 has optimized REP instruction for medium sized blocks, but for
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very small blocks it is better to use loop. For large blocks, libcall
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can do nontemporary accesses and beat inline considerably. */
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static stringop_algs bdver4_memcpy[2] = {
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{libcall, {{6, loop, false}, {14, unrolled_loop, false},
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{-1, rep_prefix_4_byte, false}}},
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{libcall, {{16, loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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static stringop_algs bdver4_memset[2] = {
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{libcall, {{8, loop, false}, {24, unrolled_loop, false},
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{2048, rep_prefix_4_byte, false}, {-1, libcall, false}}},
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{libcall, {{48, unrolled_loop, false}, {8192, rep_prefix_8_byte, false},
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{-1, libcall, false}}}};
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struct processor_costs bdver4_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (4), /* cost of starting multiply for QI */
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COSTS_N_INSNS (4), /* HI */
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COSTS_N_INSNS (4), /* SI */
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COSTS_N_INSNS (6), /* DI */
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COSTS_N_INSNS (6)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (35), /* HI */
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COSTS_N_INSNS (51), /* SI */
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COSTS_N_INSNS (83), /* DI */
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COSTS_N_INSNS (83)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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9, /* MOVE_RATIO */
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/* All move costs are relative to integer->integer move times 2 and thus
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they are latency*2. */
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8, /* cost for loading QImode using movzbl */
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{8, 8, 8}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer registers */
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4, /* cost of reg,reg fld/fst */
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{12, 12, 28}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{10, 10, 18}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode */
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4, /* cost of moving MMX register */
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{12, 12}, /* cost of loading MMX registers
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in SImode and DImode */
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{10, 10}, /* cost of storing MMX registers
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in SImode and DImode */
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2, 4, 8, /* cost of moving XMM,YMM,ZMM register */
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{12, 12, 10, 20, 30}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit */
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{12, 12, 10, 20, 30}, /* cost of unaligned loads. */
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{10, 10, 10, 20, 30}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit */
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{10, 10, 10, 20, 30}, /* cost of unaligned stores. */
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16, 20, /* SSE->integer and integer->SSE moves */
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12, 12, /* Gather load static, per_elt. */
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10, 10, /* Gather store static, per_elt. */
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16, /* size of l1 cache. */
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2048, /* size of l2 cache. */
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64, /* size of prefetch block */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
|
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
|
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time). */
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100, /* number of parallel prefetches */
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2, /* Branch cost */
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COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (6), /* cost of FMUL instruction. */
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COSTS_N_INSNS (42), /* cost of FDIV instruction. */
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COSTS_N_INSNS (2), /* cost of FABS instruction. */
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COSTS_N_INSNS (2), /* cost of FCHS instruction. */
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COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (2), /* cost of cheap SSE instruction. */
|
||||
COSTS_N_INSNS (6), /* cost of ADDSS/SD SUBSS/SD insns. */
|
||||
COSTS_N_INSNS (6), /* cost of MULSS instruction. */
|
||||
COSTS_N_INSNS (6), /* cost of MULSD instruction. */
|
||||
COSTS_N_INSNS (6), /* cost of FMA SS instruction. */
|
||||
COSTS_N_INSNS (6), /* cost of FMA SD instruction. */
|
||||
/* 9-24 */
|
||||
COSTS_N_INSNS (24), /* cost of DIVSS instruction. */
|
||||
/* 9-27 */
|
||||
COSTS_N_INSNS (27), /* cost of DIVSD instruction. */
|
||||
COSTS_N_INSNS (15), /* cost of SQRTSS instruction. */
|
||||
COSTS_N_INSNS (26), /* cost of SQRTSD instruction. */
|
||||
1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */
|
||||
bdver4_memcpy,
|
||||
bdver4_memset,
|
||||
bdver_memcpy,
|
||||
bdver_memset,
|
||||
COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
|
||||
COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
|
||||
"16:11:8", /* Loop alignment. */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue