[x86] Don't use builtins for unaligned load/store
2016-08-31 Marc Glisse <marc.glisse@inria.fr> gcc/ * config/i386/avx512fintrin.h (__m512_u, __m512i_u, __m512d_u): New types. (_mm512_loadu_pd, _mm512_storeu_pd, _mm512_loadu_ps, _mm512_storeu_ps, _mm512_loadu_si512, _mm512_storeu_si512): Replace builtin with vector extension. * config/i386/avxintrin.h (__m256_u, __m256i_u, __m256d_u): New types. (_mm256_loadu_pd, _mm256_storeu_pd, _mm256_loadu_ps, _mm256_storeu_ps, _mm256_loadu_si256, _mm256_storeu_si256): Replace builtin with vector extension. * config/i386/emmintrin.h (__m128i_u, __m128d_u): New types. (_mm_loadu_pd, _mm_storeu_pd, _mm_loadu_si128, _mm_storeu_si128): Replace builtin with vector extension. * config/i386/xmmintrin.h (__m128_u): New type. (_mm_loadu_ps, _mm_storeu_ps): Replace builtin with vector extension. (_mm_load_ps, _mm_store_ps): Simplify. gcc/testsuite/ * gcc.target/i386/pr59539-2.c: Adapt options. * gcc.target/i386/avx512f-vmovdqu32-1.c: Relax expected asm. From-SVN: r239889
This commit is contained in:
Marc Glisse
Marc Glisse
parent
c1105fa7e4
commit
c6b0037d0e
8 changed files with 74 additions and 39 deletions
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@ -1,3 +1,22 @@
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2016-08-31 Marc Glisse <marc.glisse@inria.fr>
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* config/i386/avx512fintrin.h (__m512_u, __m512i_u, __m512d_u):
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New types.
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(_mm512_loadu_pd, _mm512_storeu_pd, _mm512_loadu_ps,
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_mm512_storeu_ps, _mm512_loadu_si512, _mm512_storeu_si512):
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Replace builtin with vector extension.
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* config/i386/avxintrin.h (__m256_u, __m256i_u, __m256d_u):
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New types.
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(_mm256_loadu_pd, _mm256_storeu_pd, _mm256_loadu_ps,
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_mm256_storeu_ps, _mm256_loadu_si256, _mm256_storeu_si256):
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Replace builtin with vector extension.
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* config/i386/emmintrin.h (__m128i_u, __m128d_u): New types.
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(_mm_loadu_pd, _mm_storeu_pd, _mm_loadu_si128, _mm_storeu_si128):
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Replace builtin with vector extension.
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* config/i386/xmmintrin.h (__m128_u): New type.
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(_mm_loadu_ps, _mm_storeu_ps): Replace builtin with vector extension.
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(_mm_load_ps, _mm_store_ps): Simplify.
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2016-08-31 Eric Botcazou <ebotcazou@adacore.com>
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* config/arm/arm.c (thumb1_size_rtx_costs) <SET>: Add missing guard.
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@ -52,6 +52,11 @@ typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
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typedef long long __m512i __attribute__ ((__vector_size__ (64), __may_alias__));
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typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
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/* Unaligned version of the same type. */
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typedef float __m512_u __attribute__ ((__vector_size__ (64), __may_alias__, __aligned__ (1)));
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typedef long long __m512i_u __attribute__ ((__vector_size__ (64), __may_alias__, __aligned__ (1)));
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typedef double __m512d_u __attribute__ ((__vector_size__ (64), __may_alias__, __aligned__ (1)));
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typedef unsigned char __mmask8;
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typedef unsigned short __mmask16;
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@ -5674,10 +5679,7 @@ extern __inline __m512d
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_loadu_pd (void const *__P)
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{
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return (__m512d) __builtin_ia32_loadupd512_mask ((const double *) __P,
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(__v8df)
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_mm512_undefined_pd (),
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(__mmask8) -1);
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return *(__m512d_u *)__P;
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}
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extern __inline __m512d
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@ -5703,8 +5705,7 @@ extern __inline void
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_storeu_pd (void *__P, __m512d __A)
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{
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__builtin_ia32_storeupd512_mask ((double *) __P, (__v8df) __A,
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(__mmask8) -1);
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*(__m512d_u *)__P = __A;
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}
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extern __inline void
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@ -5719,10 +5720,7 @@ extern __inline __m512
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_loadu_ps (void const *__P)
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{
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return (__m512) __builtin_ia32_loadups512_mask ((const float *) __P,
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(__v16sf)
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_mm512_undefined_ps (),
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(__mmask16) -1);
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return *(__m512_u *)__P;
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}
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extern __inline __m512
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@ -5748,8 +5746,7 @@ extern __inline void
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_storeu_ps (void *__P, __m512 __A)
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{
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__builtin_ia32_storeups512_mask ((float *) __P, (__v16sf) __A,
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(__mmask16) -1);
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*(__m512_u *)__P = __A;
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}
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extern __inline void
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@ -5791,10 +5788,7 @@ extern __inline __m512i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_loadu_si512 (void const *__P)
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{
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return (__m512i) __builtin_ia32_loaddqusi512_mask ((const int *) __P,
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(__v16si)
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_mm512_setzero_si512 (),
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(__mmask16) -1);
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return *(__m512i_u *)__P;
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}
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extern __inline __m512i
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@ -5820,8 +5814,7 @@ extern __inline void
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_storeu_si512 (void *__P, __m512i __A)
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{
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__builtin_ia32_storedqusi512_mask ((int *) __P, (__v16si) __A,
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(__mmask16) -1);
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*(__m512i_u *)__P = __A;
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}
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extern __inline void
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@ -58,6 +58,17 @@ typedef long long __m256i __attribute__ ((__vector_size__ (32),
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typedef double __m256d __attribute__ ((__vector_size__ (32),
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__may_alias__));
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/* Unaligned version of the same types. */
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typedef float __m256_u __attribute__ ((__vector_size__ (32),
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__may_alias__,
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__aligned__ (1)));
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typedef long long __m256i_u __attribute__ ((__vector_size__ (32),
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__may_alias__,
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__aligned__ (1)));
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typedef double __m256d_u __attribute__ ((__vector_size__ (32),
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__may_alias__,
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__aligned__ (1)));
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/* Compare predicates for scalar and packed compare intrinsics. */
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/* Equal (ordered, non-signaling) */
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@ -857,25 +868,25 @@ _mm256_store_ps (float *__P, __m256 __A)
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extern __inline __m256d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_loadu_pd (double const *__P)
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{
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return (__m256d) __builtin_ia32_loadupd256 (__P);
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return *(__m256d_u *)__P;
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_storeu_pd (double *__P, __m256d __A)
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{
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__builtin_ia32_storeupd256 (__P, (__v4df)__A);
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*(__m256d_u *)__P = __A;
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}
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extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_loadu_ps (float const *__P)
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{
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return (__m256) __builtin_ia32_loadups256 (__P);
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return *(__m256_u *)__P;
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_storeu_ps (float *__P, __m256 __A)
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{
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__builtin_ia32_storeups256 (__P, (__v8sf)__A);
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*(__m256_u *)__P = __A;
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}
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extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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@ -891,15 +902,15 @@ _mm256_store_si256 (__m256i *__P, __m256i __A)
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}
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extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_loadu_si256 (__m256i const *__P)
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_mm256_loadu_si256 (__m256i_u const *__P)
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{
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return (__m256i) __builtin_ia32_loaddqu256 ((char const *)__P);
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return *__P;
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_storeu_si256 (__m256i *__P, __m256i __A)
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_mm256_storeu_si256 (__m256i_u *__P, __m256i __A)
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{
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__builtin_ia32_storedqu256 ((char *)__P, (__v32qi)__A);
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*__P = __A;
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}
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extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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@ -52,6 +52,10 @@ typedef unsigned char __v16qu __attribute__ ((__vector_size__ (16)));
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typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
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typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
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/* Unaligned version of the same types. */
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typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
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typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
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/* Create a selector for use with the SHUFPD instruction. */
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#define _MM_SHUFFLE2(fp1,fp0) \
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(((fp1) << 1) | (fp0))
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@ -123,7 +127,7 @@ _mm_load_pd (double const *__P)
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extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_loadu_pd (double const *__P)
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{
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return __builtin_ia32_loadupd (__P);
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return *(__m128d_u *)__P;
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}
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/* Create a vector with all two elements equal to *P. */
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@ -165,7 +169,7 @@ _mm_store_pd (double *__P, __m128d __A)
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_storeu_pd (double *__P, __m128d __A)
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{
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__builtin_ia32_storeupd (__P, __A);
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*(__m128d_u *)__P = __A;
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}
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/* Stores the lower DPFP value. */
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@ -693,9 +697,9 @@ _mm_load_si128 (__m128i const *__P)
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}
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extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_loadu_si128 (__m128i const *__P)
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_mm_loadu_si128 (__m128i_u const *__P)
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{
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return (__m128i) __builtin_ia32_loaddqu ((char const *)__P);
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return *__P;
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}
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extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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@ -711,9 +715,9 @@ _mm_store_si128 (__m128i *__P, __m128i __B)
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_storeu_si128 (__m128i *__P, __m128i __B)
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_mm_storeu_si128 (__m128i_u *__P, __m128i __B)
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{
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__builtin_ia32_storedqu ((char *)__P, (__v16qi)__B);
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*__P = __B;
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}
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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@ -68,6 +68,9 @@ _mm_prefetch (const void *__P, enum _mm_hint __I)
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vector types, and their scalar components. */
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typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
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/* Unaligned version of the same type. */
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typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
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/* Internal data types for implementing the intrinsics. */
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typedef float __v4sf __attribute__ ((__vector_size__ (16)));
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@ -921,14 +924,14 @@ _mm_load_ps1 (float const *__P)
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extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_load_ps (float const *__P)
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{
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return (__m128) *(__v4sf *)__P;
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return *(__m128 *)__P;
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}
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/* Load four SPFP values from P. The address need not be 16-byte aligned. */
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extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_loadu_ps (float const *__P)
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{
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return (__m128) __builtin_ia32_loadups (__P);
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return *(__m128_u *)__P;
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}
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/* Load four SPFP values in reverse order. The address must be aligned. */
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@ -970,14 +973,14 @@ _mm_cvtss_f32 (__m128 __A)
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_store_ps (float *__P, __m128 __A)
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{
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*(__v4sf *)__P = (__v4sf)__A;
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*(__m128 *)__P = __A;
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}
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/* Store four SPFP values. The address need not be 16-byte aligned. */
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_storeu_ps (float *__P, __m128 __A)
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{
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__builtin_ia32_storeups (__P, (__v4sf)__A);
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*(__m128_u *)__P = __A;
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}
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/* Store the lower SPFP value across four words. */
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@ -1,3 +1,8 @@
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2016-08-31 Marc Glisse <marc.glisse@inria.fr>
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* gcc.target/i386/pr59539-2.c: Adapt options.
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* gcc.target/i386/avx512f-vmovdqu32-1.c: Relax expected asm.
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2016-08-31 Paul Thomas <pault@gcc.gnu.org>
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PR fortran/77418
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vmovdqu\[36\]\[24\]\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu(?:32|64)\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\{\n\]*\\)\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu(?:32|64)\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* PR target/59539 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx2" } */
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/* { dg-options "-O2 -march=haswell" } */
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#include <immintrin.h>
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