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aarch64: Add some uses of force_highpart_subreg

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This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.

gcc/
	* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
	force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
	(aarch64_subvti_scratch_regs): Likewise.
This commit is contained in:
Richard Sandiford 2024-06-18 12:22:33 +01:00
parent e0700fbe35
commit c67a9a9c8e
1 changed files with 4 additions and 13 deletions
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17
gcc/config/aarch64/aarch64.cc
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@ -26873,19 +26873,12 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
*low_in1 = force_lowpart_subreg (DImode, op1, TImode);
*low_in2 = force_lowpart_subreg (DImode, op2, TImode);
*high_dest = gen_reg_rtx (DImode);
*high_in1 = gen_highpart (DImode, op1);
*high_in2 = simplify_gen_subreg (DImode, op2, TImode,
subreg_highpart_offset (DImode, TImode));
*high_in1 = force_highpart_subreg (DImode, op1, TImode);
*high_in2 = force_highpart_subreg (DImode, op2, TImode);
}
/* Generate DImode scratch registers for 128-bit (TImode) subtraction.
This function differs from 'arch64_addti_scratch_regs' in that
OP1 can be an immediate constant (zero). We must call
subreg_highpart_offset with DImode and TImode arguments, otherwise
VOIDmode will be used for the const_int which generates an internal
error from subreg_size_highpart_offset which does not expect a size of zero.
OP1 represents the TImode destination operand 1
OP2 represents the TImode destination operand 2
LOW_DEST represents the low half (DImode) of TImode operand 0
@ -26907,10 +26900,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
*low_in2 = force_lowpart_subreg (DImode, op2, TImode);
*high_dest = gen_reg_rtx (DImode);
*high_in1 = simplify_gen_subreg (DImode, op1, TImode,
subreg_highpart_offset (DImode, TImode));
*high_in2 = simplify_gen_subreg (DImode, op2, TImode,
subreg_highpart_offset (DImode, TImode));
*high_in1 = force_highpart_subreg (DImode, op1, TImode);
*high_in2 = force_highpart_subreg (DImode, op2, TImode);
}
/* Generate RTL for 128-bit (TImode) subtraction with overflow.