tree-optimization/110897 - Fix missed vectorization of shift on both RISC-V and aarch64
Consider this following case: #include <stdint.h> #define TEST2_TYPE(TYPE) \ __attribute__((noipa)) \ void vshiftr_##TYPE (TYPE *__restrict dst, TYPE *__restrict a, TYPE *__restrict b, int n) \ { \ for (int i = 0; i < n; i++) \ dst[i] = (a[i]) >> b[i]; \ } #define TEST_ALL() \ TEST2_TYPE(uint8_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(uint32_t) \ TEST2_TYPE(uint64_t) \ TEST_ALL() Both RISC-V and aarch64 of trunk GCC failed vectorize uint8_t/uint16_t with following missed report: <source>:17:1: missed: couldn't vectorize loop <source>:17:1: missed: not vectorized: relevant stmt not supported: patt_46 = MIN_EXPR <_6, 7>; <source>:17:1: missed: couldn't vectorize loop <source>:17:1: missed: not vectorized: relevant stmt not supported: patt_47 = MIN_EXPR <_7, 15>; Compiler returned: 0 Both GCC 13.1 can vectorize, see: https://godbolt.org/z/6vaMK5M1o Bootstrap and regression on X86 passed. Ok for trunk ? gcc/ChangeLog: * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Add op vectype. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Adapt testcase.
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2 changed files with 4 additions and 3 deletions
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@ -27,5 +27,5 @@
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TEST_ALL ()
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/* { dg-final { scan-assembler-times {\tvnsra\.wv} 6 } } */
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/* { dg-final { scan-assembler-times {\tvnsrl\.wv} 5 } } */
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/* { dg-final { scan-assembler-times {\tvnsra\.wv} 4 } } */
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/* { dg-final { scan-assembler-times {\tvnsrl\.wv} 4 } } */
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@ -3133,7 +3133,8 @@ vect_recog_over_widening_pattern (vec_info *vinfo,
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return NULL;
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}
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else
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append_pattern_def_seq (vinfo, last_stmt_info, pattern_stmt);
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append_pattern_def_seq (vinfo, last_stmt_info, pattern_stmt,
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op_vectype);
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ops[1] = new_var;
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}
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}
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