s390-protos.h (s390_split_access_reg): Add prototype.
* config/s390/s390-protos.h (s390_split_access_reg): Add prototype.
* config/s390/s390.c (s390_split_access_reg): New function.
(regclass_map): Add access registers.
(get_thread_pointer): Use access register instead of UNSPEC_TP.
* config/s390/s390.h (FIRST_PSEUDO_REGISTER): Set to 38.
(ACCESS_REGNO_P, ACCESS_REG_P): New macros.
(TP_REGNUM): New define.
(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS,
REG_ALLOC_ORDER): Add access registers.
(HARD_REGNO_NREGS, HARD_REGNO_MODE_OK, CLASS_MAX_NREGS,
CANNOT_CHANGE_MODE_CLASS): Support access registers.
(enum reg_class): Add ACCESS_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Likewise.
(REG_CLASS_FROM_LETTER): Add 't' constraint.
(REGISTER_NAMES): Add access registers.
* config/s390/s390.md (UNSPEC_TP): Remove.
("*movdi_64"): Add access register alternatives. Provide splitters
to split DImode access register <-> GPR moves into SImode moves.
("*movsi_zarch", "*movsi_esa"): Add access register alternatives.
("movstrictsi"): Likewise.
("get_tp_64", "get_tp_31"): Reimplement using access registers.
("set_tp_64", "set_tp_31"): Likewise.
("*set_tp"): New insn.
From-SVN: r90036
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
57f60923b2
commit
c5aa1d125c
5 changed files with 176 additions and 76 deletions
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@ -1,3 +1,29 @@
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2004-11-03 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390-protos.h (s390_split_access_reg): Add prototype.
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* config/s390/s390.c (s390_split_access_reg): New function.
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(regclass_map): Add access registers.
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(get_thread_pointer): Use access register instead of UNSPEC_TP.
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* config/s390/s390.h (FIRST_PSEUDO_REGISTER): Set to 38.
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(ACCESS_REGNO_P, ACCESS_REG_P): New macros.
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(TP_REGNUM): New define.
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(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS,
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REG_ALLOC_ORDER): Add access registers.
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(HARD_REGNO_NREGS, HARD_REGNO_MODE_OK, CLASS_MAX_NREGS,
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CANNOT_CHANGE_MODE_CLASS): Support access registers.
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(enum reg_class): Add ACCESS_REGS.
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(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Likewise.
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(REG_CLASS_FROM_LETTER): Add 't' constraint.
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(REGISTER_NAMES): Add access registers.
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* config/s390/s390.md (UNSPEC_TP): Remove.
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("*movdi_64"): Add access register alternatives. Provide splitters
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to split DImode access register <-> GPR moves into SImode moves.
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("*movsi_zarch", "*movsi_esa"): Add access register alternatives.
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("movstrictsi"): Likewise.
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("get_tp_64", "get_tp_31"): Reimplement using access registers.
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("set_tp_64", "set_tp_31"): Likewise.
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("*set_tp"): New insn.
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2004-11-03 Kazu Hirata <kazu@cs.umass.edu>
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* tree-phinodes.c (resize_phi_node): Copy only a portion of
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@ -90,6 +90,7 @@ extern void s390_expand_logical_operator (enum rtx_code,
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extern bool s390_logical_operator_ok_p (rtx *);
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extern void s390_narrow_logical_operator (enum rtx_code, rtx *, rtx *);
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extern bool s390_pool_operand (rtx);
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extern void s390_split_access_reg (rtx, rtx *, rtx *);
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extern bool s390_output_addr_const_extra (FILE*, rtx);
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extern void print_operand_address (FILE *, rtx);
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@ -1355,7 +1355,8 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS
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ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
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ACCESS_REGS, ACCESS_REGS
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};
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/* Return attribute type of insn. */
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@ -2019,6 +2020,22 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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return 1;
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}
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/* Split DImode access register reference REG (on 64-bit) into its constituent
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low and high parts, and store them into LO and HI. Note that gen_lowpart/
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gen_highpart cannot be used as they assume all registers are word-sized,
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while our access registers have only half that size. */
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void
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s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
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{
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gcc_assert (TARGET_64BIT);
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gcc_assert (ACCESS_REG_P (reg));
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gcc_assert (GET_MODE (reg) == DImode);
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gcc_assert (!(REGNO (reg) & 1));
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*lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
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*hi = gen_rtx_REG (SImode, REGNO (reg));
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}
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/* Return true if OP contains a symbol reference */
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@ -3033,10 +3050,9 @@ legitimize_pic_address (rtx orig, rtx reg)
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static rtx
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get_thread_pointer (void)
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{
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rtx tp;
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rtx tp = gen_reg_rtx (Pmode);
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tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
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tp = force_reg (Pmode, tp);
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emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
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mark_reg_pointer (tp, BITS_PER_WORD);
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return tp;
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@ -307,13 +307,17 @@ if (INTEGRAL_MODE_P (MODE) && \
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GPR 14: Return address register
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GPR 15: Stack pointer
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Registers 32-34 are 'fake' hard registers that do not
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Registers 32-35 are 'fake' hard registers that do not
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correspond to actual hardware:
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Reg 32: Argument pointer
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Reg 33: Condition code
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Reg 34: Frame pointer */
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Reg 34: Frame pointer
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Reg 35: Return address pointer
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#define FIRST_PSEUDO_REGISTER 36
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Registers 36 and 37 are mapped to access registers
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0 and 1, used to implement thread-local storage. */
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#define FIRST_PSEUDO_REGISTER 38
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/* Standard register usage. */
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#define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
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@ -321,17 +325,20 @@ if (INTEGRAL_MODE_P (MODE) && \
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#define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
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#define CC_REGNO_P(N) ((N) == 33)
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#define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35)
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#define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37)
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#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
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#define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
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#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
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#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
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#define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
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#define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
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#define SIBCALL_REGNUM 1
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#define BASE_REGNUM 13
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#define RETURN_REGNUM 14
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#define CC_REGNUM 33
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#define TP_REGNUM 36
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/* Set up fixed registers and calling convention:
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@ -342,6 +349,7 @@ if (INTEGRAL_MODE_P (MODE) && \
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GPR 14 is always fixed on S/390 machines (as return address).
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GPR 15 is always fixed (as stack pointer).
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The 'fake' hard registers are call-clobbered and fixed.
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The access registers are call-saved and fixed.
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On 31-bit, FPRs 18-19 are call-clobbered;
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on 64-bit, FPRs 24-31 are call-clobbered.
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@ -356,7 +364,8 @@ if (INTEGRAL_MODE_P (MODE) && \
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0, 0, 0, 0, \
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0, 0, 0, 0, \
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0, 0, 0, 0, \
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1, 1, 1, 1 }
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1, 1, 1, 1, \
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1, 1 }
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#define CALL_USED_REGISTERS \
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{ 1, 1, 1, 1, \
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@ -367,7 +376,8 @@ if (INTEGRAL_MODE_P (MODE) && \
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1, 1, 1, 1, \
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1, 1, 1, 1, \
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1, 1, 1, 1, \
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1, 1, 1, 1 }
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1, 1, 1, 1, \
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1, 1 }
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#define CALL_REALLY_USED_REGISTERS \
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{ 1, 1, 1, 1, \
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@ -378,7 +388,8 @@ if (INTEGRAL_MODE_P (MODE) && \
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1, 1, 1, 1, \
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1, 1, 1, 1, \
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1, 1, 1, 1, \
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1, 1, 1, 1 }
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1, 1, 1, 1, \
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0, 0 }
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#define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
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@ -387,7 +398,7 @@ if (INTEGRAL_MODE_P (MODE) && \
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{ 1, 2, 3, 4, 5, 0, 13, 12, 11, 10, 9, 8, 7, 6, 14, \
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16, 17, 18, 19, 20, 21, 22, 23, \
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24, 25, 26, 27, 28, 29, 30, 31, \
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15, 32, 33, 34, 35 }
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15, 32, 33, 34, 35, 36, 37 }
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/* Fitting values into registers. */
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@ -411,6 +422,8 @@ if (INTEGRAL_MODE_P (MODE) && \
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(GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
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GENERAL_REGNO_P(REGNO)? \
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((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
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ACCESS_REGNO_P(REGNO)? \
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((GET_MODE_SIZE(MODE)+32-1) / 32) : \
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1)
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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@ -424,6 +437,9 @@ if (INTEGRAL_MODE_P (MODE) && \
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GET_MODE_CLASS (MODE) == MODE_CC : \
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FRAME_REGNO_P(REGNO)? \
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(enum machine_mode) (MODE) == Pmode : \
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ACCESS_REGNO_P(REGNO)? \
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(((MODE) == SImode || ((enum machine_mode) (MODE) == Pmode)) \
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&& (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1))) : \
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0)
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#define MODES_TIEABLE_P(MODE1, MODE2) \
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@ -435,48 +451,54 @@ if (INTEGRAL_MODE_P (MODE) && \
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((CLASS) == FP_REGS ? \
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(GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
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(CLASS) == ACCESS_REGS ? \
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(GET_MODE_SIZE (MODE) + 32 - 1) / 32 : \
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(GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* If a 4-byte value is loaded into a FPR, it is placed into the
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*upper* half of the register, not the lower. Therefore, we
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cannot use SUBREGs to switch between modes in FP registers. */
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cannot use SUBREGs to switch between modes in FP registers.
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Likewise for access registers, since they have only half the
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word size on 64-bit. */
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#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
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? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
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? reg_classes_intersect_p (FP_REGS, CLASS) \
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|| reg_classes_intersect_p (ACCESS_REGS, CLASS) : 0)
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/* Register classes. */
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/* We use the following register classes:
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GENERAL_REGS All general purpose registers
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CC_REGS Contains only the condition code register
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ADDR_REGS All general purpose registers except %r0
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(These registers can be used in address generation)
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ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
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GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
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FP_REGS All floating point registers
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CC_REGS The condition code register
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ACCESS_REGS The access registers
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GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
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ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
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GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
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ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
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NO_REGS No registers
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ALL_REGS All registers
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Note that the 'fake' frame pointer and argument pointer registers
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are included amongst the address registers here. The condition
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code register is only included in ALL_REGS. */
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are included amongst the address registers here. */
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enum reg_class
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{
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NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS,
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NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
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ADDR_CC_REGS, GENERAL_CC_REGS,
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FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
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ALL_REGS, LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ADDR_CC_REGS", \
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"GENERAL_CC_REGS", "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \
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"ADDR_CC_REGS", "GENERAL_CC_REGS", \
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"FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
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/* Class -> register mapping. */
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#define REG_CLASS_CONTENTS \
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@ -485,12 +507,13 @@ enum reg_class
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{ 0x00000000, 0x00000002 }, /* CC_REGS */ \
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{ 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \
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{ 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \
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{ 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \
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{ 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \
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{ 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \
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{ 0xffff0000, 0x00000000 }, /* FP_REGS */ \
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{ 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \
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{ 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \
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{ 0xffffffff, 0x0000000f }, /* ALL_REGS */ \
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{ 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
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}
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/* Register -> class mapping. */
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@ -543,7 +566,8 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
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((C) == 'a' ? ADDR_REGS : \
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(C) == 'd' ? GENERAL_REGS : \
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(C) == 'f' ? FP_REGS : \
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(C) == 'c' ? CC_REGS : NO_REGS)
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(C) == 'c' ? CC_REGS : \
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(C) == 't' ? ACCESS_REGS : NO_REGS)
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#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
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s390_const_ok_for_constraint_p ((VALUE), (C), (STR))
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@ -976,7 +1000,7 @@ extern int flag_pic;
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"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
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"%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
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"%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
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"%ap", "%cc", "%fp", "%rp" \
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"%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \
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}
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/* Emit a dtp-relative reference to a TLS variable. */
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@ -112,7 +112,6 @@
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(UNSPEC_INDNTPOFF 505)
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; TLS support
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(UNSPEC_TP 510)
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(UNSPEC_TLSLDM_NTPOFF 511)
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(UNSPEC_TLS_LOAD 512)
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@ -887,9 +886,9 @@
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(define_insn "*movdi_64"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q")
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"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
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(match_operand:DI 1 "general_operand"
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"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))]
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"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
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"TARGET_64BIT"
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"@
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lghi\t%0,%h1
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@ -906,10 +905,47 @@
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ldy\t%0,%1
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std\t%1,%0
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stdy\t%1,%0
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#
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#
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stam\t%1,%N1,%S0
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lam\t%0,%N0,%S1
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#"
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[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
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[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,NN,NN,RS,RS,SS")
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(set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd,
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fstored,fstored,cs")])
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fstored,fstored,*,*,*,*,cs")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(match_operand:DI 1 "register_operand" ""))]
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"TARGET_64BIT && ACCESS_REG_P (operands[1])"
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[(set (match_dup 2) (match_dup 3))
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(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
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(set (strict_low_part (match_dup 2)) (match_dup 4))]
|
||||
"operands[2] = gen_lowpart (SImode, operands[0]);
|
||||
s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && ACCESS_REG_P (operands[0])
|
||||
&& dead_or_set_p (insn, operands[1])"
|
||||
[(set (match_dup 3) (match_dup 2))
|
||||
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
|
||||
(set (match_dup 4) (match_dup 2))]
|
||||
"operands[2] = gen_lowpart (SImode, operands[1]);
|
||||
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && ACCESS_REG_P (operands[0])
|
||||
&& !dead_or_set_p (insn, operands[1])"
|
||||
[(set (match_dup 3) (match_dup 2))
|
||||
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
|
||||
(set (match_dup 4) (match_dup 2))
|
||||
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
|
||||
"operands[2] = gen_lowpart (SImode, operands[1]);
|
||||
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
|
||||
|
||||
(define_insn "*movdi_31"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
|
||||
|
|
@ -1063,9 +1099,9 @@
|
|||
|
||||
(define_insn "*movsi_zarch"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand"
|
||||
"=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
|
||||
"=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
|
||||
(match_operand:SI 1 "general_operand"
|
||||
"K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
|
||||
"K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
|
||||
"TARGET_ZARCH"
|
||||
"@
|
||||
lhi\t%0,%h1
|
||||
|
|
@ -1082,13 +1118,17 @@
|
|||
ley\t%0,%1
|
||||
ste\t%1,%0
|
||||
stey\t%1,%0
|
||||
ear\t%0,%1
|
||||
sar\t%0,%1
|
||||
stam\t%1,%1,%S0
|
||||
lam\t%0,%0,%S1
|
||||
#"
|
||||
[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
|
||||
(set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
|
||||
[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
|
||||
(set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,*,*,*,*,cs")])
|
||||
|
||||
(define_insn "*movsi_esa"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q")
|
||||
(match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))]
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
|
||||
(match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
|
||||
"!TARGET_ZARCH"
|
||||
"@
|
||||
lhi\t%0,%h1
|
||||
|
|
@ -1098,9 +1138,13 @@
|
|||
ler\t%0,%1
|
||||
le\t%0,%1
|
||||
ste\t%1,%0
|
||||
ear\t%0,%1
|
||||
sar\t%0,%1
|
||||
stam\t%1,%1,%S0
|
||||
lam\t%0,%0,%S1
|
||||
#"
|
||||
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS")
|
||||
(set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")])
|
||||
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
|
||||
(set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,cs")])
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
|
|
@ -1321,15 +1365,16 @@
|
|||
;
|
||||
|
||||
(define_insn "movstrictsi"
|
||||
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
|
||||
(match_operand:SI 1 "general_operand" "d,R,T"))]
|
||||
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
|
||||
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
lr\t%0,%1
|
||||
l\t%0,%1
|
||||
ly\t%0,%1"
|
||||
[(set_attr "op_type" "RR,RX,RXY")
|
||||
(set_attr "type" "lr,load,load")])
|
||||
ly\t%0,%1
|
||||
ear\t%0,%1"
|
||||
[(set_attr "op_type" "RR,RX,RXY,RRE")
|
||||
(set_attr "type" "lr,load,load,*")])
|
||||
|
||||
;
|
||||
; movdf instruction pattern(s).
|
||||
|
|
@ -7438,46 +7483,34 @@
|
|||
;;- Thread-local storage support.
|
||||
;;
|
||||
|
||||
(define_insn "get_tp_64"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
|
||||
(unspec:DI [(const_int 0)] UNSPEC_TP))]
|
||||
(define_expand "get_tp_64"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
|
||||
stam\t%%a0,%%a1,%S0"
|
||||
[(set_attr "op_type" "NN,RS")
|
||||
(set_attr "atype" "reg,*")
|
||||
(set_attr "type" "o3,*")
|
||||
(set_attr "length" "14,*")])
|
||||
"")
|
||||
|
||||
(define_insn "get_tp_31"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
|
||||
(unspec:SI [(const_int 0)] UNSPEC_TP))]
|
||||
(define_expand "get_tp_31"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
|
||||
"!TARGET_64BIT"
|
||||
"@
|
||||
ear\t%0,%%a0
|
||||
stam\t%%a0,%%a0,%S0"
|
||||
[(set_attr "op_type" "RRE,RS")])
|
||||
"")
|
||||
|
||||
(define_insn "set_tp_64"
|
||||
[(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
|
||||
(clobber (match_scratch:SI 1 "=d,X"))]
|
||||
(define_expand "set_tp_64"
|
||||
[(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
|
||||
(unspec_volatile [(reg:DI 36)] UNSPECV_SET_TP)]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
|
||||
lam\t%%a0,%%a1,%S0"
|
||||
[(set_attr "op_type" "NN,RS")
|
||||
(set_attr "atype" "reg,*")
|
||||
(set_attr "type" "o3,*")
|
||||
(set_attr "length" "14,*")])
|
||||
"")
|
||||
|
||||
(define_insn "set_tp_31"
|
||||
[(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
|
||||
(define_expand "set_tp_31"
|
||||
[(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
|
||||
(unspec_volatile [(reg:SI 36)] UNSPECV_SET_TP)]
|
||||
"!TARGET_64BIT"
|
||||
"@
|
||||
sar\t%%a0,%0
|
||||
lam\t%%a0,%%a0,%S0"
|
||||
[(set_attr "op_type" "RRE,RS")])
|
||||
"")
|
||||
|
||||
(define_insn "*set_tp"
|
||||
[(unspec_volatile [(reg 36)] UNSPECV_SET_TP)]
|
||||
""
|
||||
""
|
||||
[(set_attr "type" "none")
|
||||
(set_attr "length" "0")])
|
||||
|
||||
(define_insn "*tls_load_64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue