[ARC] Add support for QuarkSE processor.
gcc/ 2016-11-17 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-arches.def: Add FPX quarkse instruction as valid for arcem. * config/arc/arc-c.def (__ARC_FPX_QUARK__): Define. * config/arc/arc-cpus.def (quarkse_em): Add. * config/arc/arc-options.def (FL_FPX_QUARK, FL_QUARK): Likewise. * config/arc/arc-opts.h (FPX_QK): Define. * config/arc/arc-tables.opt: Regenerate. * config/arc/arc.c (gen_compare_reg): Change. (arc_register_move_cost): Avoid Dy,Dx moves. * config/arc/arc.h (TARGET_HARD_FLOAT): Change. (TARGET_FPX_QUARK, TARGET_FP_ASSIST): Define. * config/arc/arc.md (divsf3, sqrtsf2, fix_truncsfsi2, floatsisf2): New expands. * config/arc/fpu.md (divsf3_fpu, sqrtsf2_fpu, floatsisf2_fpu) (fix_truncsfsi2_fpu): Rename. * config/arc/fpx.md (cmp_quark, cmpsf_quark_, cmpsf_quark_ord) (cmpsf_quark_uneq, cmpsf_quark_eq, divsf3_quark, sqrtsf2_quark) (fix_truncsfsi2_quark, floatsisf2_quark): New patterns. * config/arc/t-multilib: Regenerate. From-SVN: r242546
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
c867c39d8a
commit
c4014855e8
13 changed files with 208 additions and 14 deletions
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@ -1,3 +1,25 @@
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2016-11-17 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc-arches.def: Add FPX quarkse instruction as valid
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for arcem.
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* config/arc/arc-c.def (__ARC_FPX_QUARK__): Define.
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* config/arc/arc-cpus.def (quarkse_em): Add.
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* config/arc/arc-options.def (FL_FPX_QUARK, FL_QUARK): Likewise.
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* config/arc/arc-opts.h (FPX_QK): Define.
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* config/arc/arc-tables.opt: Regenerate.
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* config/arc/arc.c (gen_compare_reg): Change.
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(arc_register_move_cost): Avoid Dy,Dx moves.
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* config/arc/arc.h (TARGET_HARD_FLOAT): Change.
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(TARGET_FPX_QUARK, TARGET_FP_ASSIST): Define.
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* config/arc/arc.md (divsf3, sqrtsf2, fix_truncsfsi2, floatsisf2):
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New expands.
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* config/arc/fpu.md (divsf3_fpu, sqrtsf2_fpu, floatsisf2_fpu)
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(fix_truncsfsi2_fpu): Rename.
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* config/arc/fpx.md (cmp_quark, cmpsf_quark_, cmpsf_quark_ord)
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(cmpsf_quark_uneq, cmpsf_quark_eq, divsf3_quark, sqrtsf2_quark)
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(fix_truncsfsi2_quark, floatsisf2_quark): New patterns.
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* config/arc/t-multilib: Regenerate.
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2016-11-17 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.c (avr_print_operand_address): Use CONST_INT_P if
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@ -40,7 +40,7 @@
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ARC_ARCH ("arcem", em, FL_MPYOPT_1_6 | FL_DIVREM | FL_CD | FL_NORM \
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| FL_BS | FL_SWAP | FL_FPUS | FL_SPFP | FL_DPFP \
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| FL_SIMD | FL_FPUDA, 0)
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| FL_SIMD | FL_FPUDA | FL_QUARK, 0)
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ARC_ARCH ("archs", hs, FL_MPYOPT_7_9 | FL_DIVREM | FL_NORM | FL_CD \
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| FL_ATOMIC | FL_LL64 | FL_BS | FL_SWAP \
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| FL_FPUS | FL_FPUD, \
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@ -58,6 +58,7 @@ ARC_C_DEF ("__ARC_FPU_DP_DIV__", TARGET_FP_DP_SQRT)
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ARC_C_DEF ("__ARC_FPU_SP_FMA__", TARGET_FP_SP_FUSED)
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ARC_C_DEF ("__ARC_FPU_DP_FMA__", TARGET_FP_DP_FUSED)
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ARC_C_DEF ("__ARC_FPU_ASSIST__", TARGET_FP_DP_AX)
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ARC_C_DEF ("__ARC_FPX_QUARK__", TARGET_FPX_QUARK)
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/* To be deprecated. */
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ARC_C_DEF ("__A6__", TARGET_ARC600)
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@ -51,6 +51,7 @@ ARC_CPU (em4, em, FL_CD, NONE)
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ARC_CPU (em4_dmips, em, FL_MPYOPT_2|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS, NONE)
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ARC_CPU (em4_fpus, em, FL_MPYOPT_2|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS|FL_FPU_FPUS, NONE)
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ARC_CPU (em4_fpuda, em, FL_MPYOPT_2|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS|FL_FPU_FPUDA, NONE)
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ARC_CPU (quarkse_em, em, FL_MPYOPT_3|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS|FL_FPX_QUARK|FL_SPFP|FL_DPFP, NONE)
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ARC_CPU (hs, hs, 0, NONE)
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ARC_CPU (archs, hs, FL_MPYOPT_2|FL_DIVREM|FL_LL64, NONE)
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@ -99,10 +99,12 @@ ARC_OPTX (FL_FPU_FPUD, (1ULL << 34), arc_fpu_build, FPU_FPUD, "mfpu=fpud")
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ARC_OPTX (FL_FPU_FPUD_DIV, (1ULL << 35), arc_fpu_build, FPU_FPUD_DIV, "mfpu=fpud_div")
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ARC_OPTX (FL_FPU_FPUD_FMA, (1ULL << 36), arc_fpu_build, FPU_FPUD_FMA, "mfpu=fpud_fma")
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ARC_OPTX (FL_FPU_FPUD_ALL, (1ULL << 37), arc_fpu_build, FPU_FPUD_ALL, "mfpu=fpud_all")
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ARC_OPTX (FL_FPX_QUARK, (1ULL << 38), arc_fpu_build, FPX_QK, "quarkse fp")
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ARC_OPT (FL_FPUS, (0xFULL << 26), 0, "single precission floating point")
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ARC_OPT (FL_FPUDA, (0xFFULL << 26), 0, "double precission fp assist")
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ARC_OPT (FL_FPUD, (0xF0FULL << 26), 0, "double precission floating point")
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ARC_OPT (FL_QUARK, (1ULL << 38), 0, "Quark SE fp extension")
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/* Local Variables: */
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/* mode: c */
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@ -48,6 +48,8 @@ enum processor_type
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#define FPU_DD 0x0080
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/* Double precision floating point assist operations. */
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#define FPX_DP 0x0100
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/* Quark SE floating point instructions. */
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#define FPX_QK 0x0200
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/* fpus option combi. */
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#define FPU_FPUS (FPU_SP | FPU_SC)
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@ -42,6 +42,9 @@ Enum(processor_type) String(em4_fpus) Value(PROCESSOR_em4_fpus)
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EnumValue
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Enum(processor_type) String(em4_fpuda) Value(PROCESSOR_em4_fpuda)
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EnumValue
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Enum(processor_type) String(quarkse_em) Value(PROCESSOR_quarkse_em)
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EnumValue
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Enum(processor_type) String(hs) Value(PROCESSOR_hs)
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@ -1726,6 +1726,26 @@ gen_compare_reg (rtx comparison, machine_mode omode)
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gen_rtx_REG (CC_FPXmode, 61),
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const0_rtx)));
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}
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else if (TARGET_FPX_QUARK && (cmode == SFmode))
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{
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switch (code)
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{
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case NE: case EQ: case GT: case UNLE: case GE: case UNLT:
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case UNEQ: case LTGT: case ORDERED: case UNORDERED:
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break;
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case LT: case UNGE: case LE: case UNGT:
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code = swap_condition (code);
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tmp = x;
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x = y;
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y = tmp;
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen_cmp_quark (cc_reg,
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gen_rtx_COMPARE (mode, x, y)));
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}
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else if (TARGET_HARD_FLOAT
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&& ((cmode == SFmode && TARGET_FP_SP_BASE)
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|| (cmode == DFmode && TARGET_FP_DP_BASE)))
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@ -7281,7 +7301,7 @@ arc_register_move_cost (machine_mode,
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return 8;
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/* Force an attempt to 'mov Dy,Dx' to spill. */
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if (TARGET_ARC700 && TARGET_DPFP
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if ((TARGET_ARC700 || TARGET_EM) && TARGET_DPFP
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&& from_class == DOUBLE_REGS && to_class == DOUBLE_REGS)
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return 100;
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@ -197,12 +197,7 @@ extern const char *arc_cpu_to_as (int argc, const char **argv);
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default for A7, and only for pre A7 cores when -mnorm is given. */
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#define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS)
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/* Indicate if an optimized floating point emulation library is available. */
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#define TARGET_OPTFPE \
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(TARGET_ARC700 \
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/* We need a barrel shifter and NORM. */ \
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|| (TARGET_ARC600 && TARGET_NORM_SET) \
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|| TARGET_HS \
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|| (TARGET_EM && TARGET_NORM_SET && TARGET_BARREL_SHIFTER))
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#define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK)
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/* Non-zero means the cpu supports swap instruction. This flag is set by
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default for A7, and only for pre A7 cores when -mswap is given. */
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@ -1702,7 +1697,7 @@ enum
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/* FPU defines. */
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/* Any FPU support. */
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#define TARGET_HARD_FLOAT (arc_fpu_build != 0)
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#define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0)
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/* Single precision floating point support. */
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#define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0)
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/* Double precision floating point support. */
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@ -1721,5 +1716,8 @@ enum
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#define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0)
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/* Double precision floating point assist instruction support. */
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#define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0)
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/* Custom FP instructions used by QuarkSE EM cpu. */
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#define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \
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&& (arc_fpu_build == FPX_QK))
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#endif /* GCC_ARC_H */
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@ -5995,6 +5995,52 @@
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gcc_unreachable ();
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")
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;;div
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(define_expand "divsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(div:SF (match_operand:SF 1 "nonmemory_operand" "")
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(match_operand:SF 2 "nonmemory_operand" "")))]
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"TARGET_FPX_QUARK || TARGET_FP_SP_SQRT"
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"
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if (TARGET_FPX_QUARK)
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{
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operands[1] = force_reg (SFmode, operands[1]);
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operands[2] = force_reg (SFmode, operands[2]);
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}
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else
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{
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if (!register_operand (operands[1], SFmode)
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&& !register_operand (operands[2], SFmode))
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operands[1] = force_reg (SFmode, operands[1]);
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}
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")
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;; Square root
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(define_expand "sqrtsf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(sqrt:SF (match_operand:SF 1 "nonmemory_operand" "")))]
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"TARGET_FPX_QUARK || TARGET_FP_SP_SQRT"
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"
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if (TARGET_FPX_QUARK)
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{
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operands[1] = force_reg (SFmode, operands[1]);
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}
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")
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;; SF->SI (using rounding towards zero)
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(define_expand "fix_truncsfsi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(fix:SI (fix:SF (match_operand:SF 1 "register_operand" ""))))]
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"TARGET_FPX_QUARK || TARGET_FP_SP_CONV"
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"")
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;; SI->SF
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(define_expand "floatsisf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:SI 1 "register_operand" "")))]
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"TARGET_FPX_QUARK || TARGET_FP_SP_CONV"
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"")
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(define_expand "extzv"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "")
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@ -215,7 +215,7 @@
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;; see pattern in arc.md
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;; Square root
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(define_insn "sqrtsf2"
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(define_insn "sqrtsf2_fpu"
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[(set (match_operand:SF 0 "register_operand" "=r,r")
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(sqrt:SF (match_operand:SF 1 "nonmemory_operand" "r,F")))]
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"TARGET_FP_SP_SQRT"
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@ -412,7 +412,7 @@
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)
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;; SI->SF
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(define_insn "floatsisf2"
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(define_insn "floatsisf2_fpu"
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[(set (match_operand:SF 0 "register_operand" "=r,r")
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(float:SF (match_operand:SI 1 "register_operand" "0,r")))]
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"TARGET_FP_SP_CONV"
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@ -448,7 +448,7 @@
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)
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;; SF->SI (using rounding towards zero)
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(define_insn "fix_truncsfsi2"
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(define_insn "fix_truncsfsi2_fpu"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "0,r"))))]
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"TARGET_FP_SP_CONV"
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@ -614,3 +614,102 @@
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[(set_attr "type" "dpfp_addsub")
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(set_attr "length" "4,8,4,8")
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(set_attr "cpu_facility" "*,*,fpx,fpx")])
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;; Intel QUARK SE extensions
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(define_mode_iterator QUARK_CMP [CC_FP_GT CC_FP_GE])
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(define_mode_attr quark_cmp [(CC_FP_GT "gt") (CC_FP_GE "ge")])
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(define_expand "cmp_quark"
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[(parallel [(set (match_operand 0 "")
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(match_operand 1 ""))
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(clobber (match_scratch:SI 2 ""))])]
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""
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"")
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(define_insn "*cmpsf_quark_<quark_cmp>"
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[(set (reg:QUARK_CMP CC_REG)
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(compare:QUARK_CMP (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))
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(clobber (match_scratch:SI 2 "=&r"))]
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"TARGET_FPX_QUARK"
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"dsp_fp_cmp\\t%2,%0,%1\\n\\trsub.f\\t0,%2,7\\n\\tcmp.nc\\t%2,1\\n\\tcmp.hi\\t%2,3"
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[(set_attr "length" "16")
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(set_attr "cond" "set")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "*cmpsf_quark_ord"
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[(set (reg:CC_FP_ORD CC_REG)
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(compare:CC_FP_ORD (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))
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(clobber (match_scratch:SI 2 "=&r"))]
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"TARGET_FPX_QUARK"
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"dsp_fp_cmp\\t%2,%0,%1\\n\\tadd.f\\t%2,%2,-8"
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[(set_attr "length" "8")
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(set_attr "cond" "set")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "*cmpsf_quark_uneq"
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[(set (reg:CC_FP_UNEQ CC_REG)
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(compare:CC_FP_UNEQ (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))
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(clobber (match_scratch:SI 2 "=&r"))]
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"TARGET_FPX_QUARK"
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"dsp_fp_cmp\\t%2,%0,%1\\n\\ttst\\t%2,6"
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[(set_attr "length" "8")
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(set_attr "cond" "set")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "*cmpsf_quark_eq"
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[(set (reg:CC_Z CC_REG)
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(compare:CC_Z (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))
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(clobber (match_scratch:SI 2 "=&r"))]
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"TARGET_FPX_QUARK"
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"dsp_fp_cmp\\t%2,%0,%1\\n\\ttst\\t%2,0x0E"
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[(set_attr "length" "8")
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(set_attr "cond" "set")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "*divsf3_quark"
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[(set (match_operand:SF 0 "register_operand" "=r")
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(div:SF (match_operand:SF 1 "register_operand" "r")
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(match_operand:SF 2 "register_operand" "r")))]
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"TARGET_FPX_QUARK"
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"dsp_fp_div\\t%0,%1,%2"
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[(set_attr "length" "4")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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(define_insn "*sqrtsf2_quark"
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[(set (match_operand:SF 0 "register_operand" "=r")
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(sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
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"TARGET_FPX_QUARK"
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"dsp_fp_sqrt\\t%0,%1"
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[(set_attr "length" "4")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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;; SF->SI (using rounding towards zero)
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(define_insn "*fix_truncsfsi2_quark"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "r"))))]
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"TARGET_FPX_QUARK"
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"dsp_fp_flt2i\\t%0,%1"
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[(set_attr "length" "4")
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(set_attr "predicable" "no")
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(set_attr "cond" "nocond")])
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;; SI->SF
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(define_insn "*floatsisf2_quark"
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[(set (match_operand:SF 0 "register_operand" "=r")
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(float:SF (match_operand:SI 1 "register_operand" "r")))]
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"TARGET_FPX_QUARK"
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"dsp_fp_i2flt\\t%0,%1"
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[(set_attr "length" "4")
|
||||
(set_attr "predicable" "no")
|
||||
(set_attr "cond" "nocond")])
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
MULTILIB_OPTIONS = mcpu=em/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400
|
||||
MULTILIB_OPTIONS = mcpu=em/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=quarkse_em/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400
|
||||
|
||||
MULTILIB_DIRNAMES = em arcem em4 em4_dmips em4_fpus em4_fpuda hs archs hs34 hs38 hs38_linux arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400
|
||||
MULTILIB_DIRNAMES = em arcem em4 em4_dmips em4_fpus em4_fpuda quarkse_em hs archs hs34 hs38 hs38_linux arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400
|
||||
|
||||
# Aliases:
|
||||
MULTILIB_MATCHES = mcpu?arc600=mcpu?ARC600
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue