From c3d2b6bc913803d3eccacb9e354f37eef1cee212 Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong Date: Wed, 20 Sep 2023 16:07:49 +0800 Subject: [PATCH] RISC-V: Fix Demand comparison bug[VSETVL PASS] This bug is exposed when we support VLS integer conversion patterns. FAIL: c-c++-common/torture/pr53505.c execution. This is because incorrect vsetvl elimination by Phase 4: 10318: 0d207057 vsetvli zero,zero,e32,m4,ta,ma 1031c: 5e003e57 vmv.v.i v28,0 .....: ........ missed e8,m1 vsetvl 10320: 7b07b057 vmsgtu.vi v0,v16,15 10324: 03083157 vadd.vi v2,v16,-16 Regression on release version GCC no surprise difference. Committed. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Fix bug. --- gcc/config/riscv/riscv-vsetvl.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index df980b6770e..e0f61148ef3 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1799,10 +1799,11 @@ vector_insn_info::operator== (const vector_insn_info &other) const if (m_demands[i] != other.demand_p ((enum demand_type) i)) return false; - if (vector_config_insn_p (m_insn->rtl ()) - || vector_config_insn_p (other.get_insn ()->rtl ())) - if (m_insn != other.get_insn ()) - return false; + /* We should consider different INSN demands as different + expression. Otherwise, we will be doing incorrect vsetvl + elimination. */ + if (m_insn != other.get_insn ()) + return false; if (!same_avl_p (other)) return false;