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RISC-V: Expand vec abs without masking.

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Standard abs synthesis during expand is max (a, -a).  This
expansion has the advantage of avoiding masking and is thus potentially
faster than the a < 0 ? -a : a synthesis.

gcc/ChangeLog:

	* config/riscv/autovec.md (abs<mode>2): Expand via max (a, -a).

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Adjust test
	expectation.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
This commit is contained in:
Robin Dapp 2024-08-09 15:05:39 +02:00
parent a8ae8f9c2e
commit c22d57cdc5
12 changed files with 47 additions and 41 deletions
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26
gcc/config/riscv/autovec.md
View file

@ -1073,29 +1073,19 @@
[(set_attr "type" "vialu")])
;; -------------------------------------------------------------------------------
;; - [INT] ABS expansion to vmslt and vneg.
;; - [INT] ABS expansion to vneg and vmax.
;; -------------------------------------------------------------------------------
(define_insn_and_split "abs<mode>2"
(define_expand "abs<mode>2"
[(set (match_operand:V_VLSI 0 "register_operand")
(abs:V_VLSI
(match_operand:V_VLSI 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(smax:V_VLSI
(match_dup 0)
(neg:V_VLSI
(match_operand:V_VLSI 1 "register_operand"))))]
"TARGET_VECTOR"
{
rtx zero = gen_const_vec_duplicate (<MODE>mode, GEN_INT (0));
machine_mode mask_mode = riscv_vector::get_mask_mode (<MODE>mode);
rtx mask = gen_reg_rtx (mask_mode);
riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
rtx ops[] = {operands[0], mask, operands[1], operands[1]};
riscv_vector::emit_vlmax_insn (code_for_pred (NEG, <MODE>mode),
riscv_vector::UNARY_OP_TAMU, ops);
DONE;
}
[(set_attr "type" "vector")])
})
;; -------------------------------------------------------------------------------
;; ---- [FP] Unary operations

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
View file

@ -36,8 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
View file

@ -39,8 +39,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
View file

@ -36,8 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
View file

@ -36,8 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
View file

@ -31,8 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
View file

@ -34,8 +34,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
View file

@ -31,8 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
View file

@ -31,8 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vmslt + vneg.v */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
View file

@ -3,7 +3,7 @@
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
View file

@ -3,7 +3,7 @@
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
View file

@ -46,7 +46,7 @@ DEF_OP_V (neg, 256, int64_t, __builtin_abs)
DEF_OP_V (neg, 512, int64_t, __builtin_abs)
/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
/* { dg-final { scan-assembler-times {vmslt\.vi} 38 } } */
/* { dg-final { scan-assembler-times {vmax\.vv} 38 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */