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[AArch64] Rename +bitperm to +sve2-bitperm

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After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags.  The associated macro was already
__ARM_FEATURE_SVE2_BITPERM, so only the feature flag itself
needs to change.

2019-07-19  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* doc/invoke.texi: Rename the AArch64 +bitperm extension flag
	to +sve-bitperm.
	* config/aarch64/aarch64-option-extensions.def: Likewise.

From-SVN: r273600
This commit is contained in:
Richard Sandiford 2019-07-19 11:24:31 +00:00 • committed by Richard Sandiford
parent 14298fa489
commit c10abf530e
3 changed files with 16 additions and 10 deletions
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6
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2019-07-19 Richard Sandiford <richard.sandiford@arm.com>
* doc/invoke.texi: Rename the AArch64 +bitperm extension flag
to +sve-bitperm.
* config/aarch64/aarch64-option-extensions.def: Likewise.
2019-07-19 Jakub Jelinek <jakub@redhat.com>
PR middle-end/91190

18
gcc/config/aarch64/aarch64-option-extensions.def
View file

@ -58,13 +58,13 @@
/* Enabling "fp" just enables "fp".
Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
"sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
"bitperm". */
"sve2-bitperm". */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fp")
/* Enabling "simd" also enables "fp".
Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
"sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm".
*/
"sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
"sve2-bitperm". */
AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "asimd")
/* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
@ -80,7 +80,7 @@ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
/* Enabling "fp16" also enables "fp".
Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
"sve2-sha3", "sve2-sm4", and "bitperm". */
"sve2-sha3", "sve2-sm4", and "sve2-bitperm". */
AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fphp asimdhp")
/* Enabling or disabling "rcpc" only changes "rcpc". */
@ -116,7 +116,7 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, AARCH64_FL_FP | AARCH64_FL_F
/* Enabling "sve" also enables "fp16", "fp" and "simd".
Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4"
and "bitperm". */
and "sve2-bitperm". */
AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "sve")
/* Enabling/Disabling "profile" does not enable/disable any other feature. */
@ -139,7 +139,7 @@ AARCH64_OPT_EXTENSION("predres", AARCH64_FL_PREDRES, 0, 0, false, "")
/* Enabling "sve2" also enables "sve", "fp16", "fp", and "simd".
Disabling "sve2" disables "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
"bitperm". */
"sve2-bitperm". */
AARCH64_OPT_EXTENSION("sve2", AARCH64_FL_SVE2, AARCH64_FL_SVE | AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "")
/* Enabling "sve2-sm4" also enables "sm4", "simd", "fp16", "fp", "sve", and
@ -154,8 +154,8 @@ AARCH64_OPT_EXTENSION("sve2-aes", AARCH64_FL_SVE2_AES, AARCH64_FL_AES | AARCH64_
"sve2". Disabling "sve2-sha3" just disables "sve2-sha3". */
AARCH64_OPT_EXTENSION("sve2-sha3", AARCH64_FL_SVE2_SHA3, AARCH64_FL_SHA3 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
/* Enabling "bitperm" also enables "simd", "fp16", "fp", "sve", and "sve2".
Disabling "bitperm" just disables "bitperm". */
AARCH64_OPT_EXTENSION("bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
/* Enabling "sve2-bitperm" also enables "simd", "fp16", "fp", "sve", and
"sve2". Disabling "sve2-bitperm" just disables "sve2-bitperm". */
AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
#undef AARCH64_OPT_EXTENSION

2
gcc/doc/invoke.texi
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@ -16083,7 +16083,7 @@ not affect code generation. This option is enabled by default for
@item sve2
Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
instructions.
@item bitperm
@item sve2-bitperm
Enable SVE2 bitperm instructions. This also enables SVE2 instructions.
@item sve2-sm4
Enable SVE2 sm4 instructions. This also enables SVE2 instructions.