re PR target/68163 (GCC on power8 does not issue the stxsspx instruction on power8)
[gcc]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
are now unused after splitting mov{sf,sd}_hardfloat.
(f32_lr2): Likewise.
(f32_lm): Likewise.
(f32_lm2): Likewise.
(f32_li): Likewise.
(f32_li2): Likewise.
(f32_lv): Likewise.
(f32_sr): Likewise.
(f32_sr2): Likewise.
(f32_sm): Likewise.
(f32_sm2): Likewise.
(f32_si): Likewise.
(f32_si2): Likewise.
(f32_sv): Likewise.
(f32_dm): Likewise.
(f32_vsx): Likewise.
(f32_av): Likewise.
(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
For movsf, order stores so the VSX stores occur before the GPR
store which encourages the register allocator to use a traditional
FPR instead of a GPR. For movsd, order the stores so that the GPR
store comes before the VSX stores to allow the power6 to work.
This is due to the power6 not having a 32-bit integer store
instruction from a FPR.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
[gcc/testsuite]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* gcc.target/powerpc/pr68163.c: New test.
From-SVN: r247819
This commit is contained in:
Michael Meissner
Michael Meissner
parent
5285d5d357
commit
bf2a705c29
4 changed files with 308 additions and 50 deletions
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@ -1,3 +1,34 @@
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2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/68163
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* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
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are now unused after splitting mov{sf,sd}_hardfloat.
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(f32_lr2): Likewise.
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(f32_lm): Likewise.
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(f32_lm2): Likewise.
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(f32_li): Likewise.
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(f32_li2): Likewise.
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(f32_lv): Likewise.
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(f32_sr): Likewise.
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(f32_sr2): Likewise.
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(f32_sm): Likewise.
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(f32_sm2): Likewise.
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(f32_si): Likewise.
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(f32_si2): Likewise.
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(f32_sv): Likewise.
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(f32_dm): Likewise.
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(f32_vsx): Likewise.
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(f32_av): Likewise.
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(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
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For movsf, order stores so the VSX stores occur before the GPR
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store which encourages the register allocator to use a traditional
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FPR instead of a GPR. For movsd, order the stores so that the GPR
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store comes before the VSX stores to allow the power6 to work.
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This is due to the power6 not having a 32-bit integer store
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instruction from a FPR.
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(movsf_hardfloat): Likewise.
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(movsd_hardfloat): Likewise.
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2017-05-09 Martin Sebor <msebor@redhat.com>
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PR translation/80280
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@ -445,35 +445,6 @@
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(DD "wn")
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(TD "wn")])
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; Definitions for load to 32-bit fpr register
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(define_mode_attr f32_lr [(SF "f") (SD "wz")])
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(define_mode_attr f32_lr2 [(SF "wb") (SD "wn")])
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(define_mode_attr f32_lm [(SF "m") (SD "Z")])
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(define_mode_attr f32_lm2 [(SF "wY") (SD "wn")])
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(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
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(define_mode_attr f32_li2 [(SF "lxssp %0,%1") (SD "lfiwzx %0,%y1")])
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(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
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; Definitions for store from 32-bit fpr register
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(define_mode_attr f32_sr [(SF "f") (SD "wx")])
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(define_mode_attr f32_sr2 [(SF "wb") (SD "wn")])
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(define_mode_attr f32_sm [(SF "m") (SD "Z")])
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(define_mode_attr f32_sm2 [(SF "wY") (SD "wn")])
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(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
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(define_mode_attr f32_si2 [(SF "stxssp %1,%0") (SD "stfiwx %1,%y0")])
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(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwx %x1,%y0")])
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; Definitions for 32-bit fpr direct move
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; At present, the decimal modes are not allowed in the traditional altivec
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; registers, so restrict the constraints to just the traditional FPRs.
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(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
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; Definitions for 32-bit VSX
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(define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
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; Definitions for 32-bit use of altivec registers
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(define_mode_attr f32_av [(SF "wu") (SD "wn")])
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; Definitions for 64-bit VSX
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(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
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@ -7232,40 +7203,82 @@
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operands[3] = gen_int_mode (l, SImode);
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}")
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(define_insn "mov<mode>_hardfloat"
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
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"=!r, <f32_lr>, <f32_lr2>, <f32_av>, m, <f32_sm>,
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<f32_sm2>, Z, <f32_vsx>, !r, ?<f32_dm>, ?r,
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f, <f32_vsx>, !r, *c*l, !r, *h")
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(match_operand:FMOVE32 1 "input_operand"
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"m, <f32_lm>, <f32_lm2>, Z, r, <f32_sr>,
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<f32_sr2>, <f32_av>, <zero_fp>, <zero_fp>, r, <f32_dm>,
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f, <f32_vsx>, r, r, *h, 0"))]
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"(register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))
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;; Originally, we tried to keep movsf and movsd common, but the differences
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;; addressing was making it rather difficult to hide with mode attributes. In
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;; particular for SFmode, on ISA 2.07 (power8) systems, having the GPR store
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;; before the VSX stores meant that the register allocator would tend to do a
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;; direct move to the GPR (which involves conversion from scalar to
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;; vector/memory formats) to save values in the traditional Altivec registers,
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;; while SDmode had problems on power6 if the GPR store was not first due to
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;; the power6 not having an integer store operation.
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;;
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;; LWZ LFS LXSSP LXSSPX STFS STXSSP
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;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
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;; MR MT<x> MF<x> NOP
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(define_insn "movsf_hardfloat"
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[(set (match_operand:SF 0 "nonimmediate_operand"
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"=!r, f, wb, wu, m, wY,
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Z, m, ww, !r, f, ww,
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!r, *c*l, !r, *h")
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(match_operand:SF 1 "input_operand"
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"m, m, wY, Z, f, wb,
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wu, r, j, j, f, ww,
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r, r, *h, 0"))]
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"(register_operand (operands[0], SFmode)
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|| register_operand (operands[1], SFmode))
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
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&& (TARGET_ALLOW_SF_SUBREG
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|| valid_sf_si_move (operands[0], operands[1], <MODE>mode))"
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|| valid_sf_si_move (operands[0], operands[1], SFmode))"
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"@
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lwz%U1%X1 %0,%1
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<f32_li>
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<f32_li2>
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<f32_lv>
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lfs%U1%X1 %0,%1
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lxssp %0,%1
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lxsspx %x0,%y1
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stfs%U0%X0 %1,%0
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stxssp %1,%0
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stxsspx %x1,%y0
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stw%U0%X0 %1,%0
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<f32_si>
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<f32_si2>
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<f32_sv>
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xxlxor %x0,%x0,%x0
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li %0,0
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mtvsrwz %x0,%1
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mfvsrwz %0,%x1
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fmr %0,%1
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xscpsgndp %x0,%x1,%x1
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mr %0,%1
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mt%0 %1
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mf%1 %0
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nop"
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[(set_attr "type" "load,fpload,fpload,fpload,store,fpstore,fpstore,fpstore,veclogical,integer,mffgpr,mftgpr,fpsimple,fpsimple,*,mtjmpr,mfjmpr,*")])
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[(set_attr "type"
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"load, fpload, fpload, fpload, fpstore, fpstore,
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fpstore, store, veclogical, integer, fpsimple, fpsimple,
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*, mtjmpr, mfjmpr, *")])
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;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
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;; FMR MR MT%0 MF%1 NOP
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(define_insn "movsd_hardfloat"
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[(set (match_operand:SD 0 "nonimmediate_operand"
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"=!r, wz, m, Z, ?wh, ?r,
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f, !r, *c*l, !r, *h")
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(match_operand:SD 1 "input_operand"
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"m, Z, r, wx, r, wh,
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f, r, r, *h, 0"))]
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"(register_operand (operands[0], SDmode)
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|| register_operand (operands[1], SDmode))
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"@
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lwz%U1%X1 %0,%1
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lfiwzx %0,%y1
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stw%U0%X0 %1,%0
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stfiwx %1,%y0
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mtvsrwz %x0,%1
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mfvsrwz %0,%x1
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fmr %0,%1
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mr %0,%1
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mt%0 %1
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mf%1 %0
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nop"
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[(set_attr "type"
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"load, fpload, store, fpstore, mffgpr, mftgpr,
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fpsimple, *, mtjmpr, mfjmpr, *")])
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(define_insn "*mov<mode>_softfloat"
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
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@ -1,3 +1,8 @@
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2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/68163
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* gcc.target/powerpc/pr68163.c: New test.
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2017-05-09 Janus Weil <janus@gcc.gnu.org>
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PR fortran/79311
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209
gcc/testsuite/gcc.target/powerpc/pr68163.c
Normal file
209
gcc/testsuite/gcc.target/powerpc/pr68163.c
Normal file
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@ -0,0 +1,209 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-mcpu=power8 -O2" } */
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/* Make sure that the register allocator does not move SF values to GPR
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registers in order to do an offsettable store. */
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#ifndef TYPE
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#define TYPE float
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#endif
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#ifndef TYPE_IN
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#define TYPE_IN TYPE
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#endif
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#ifndef TYPE_OUT
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#define TYPE_OUT TYPE
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#endif
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#ifndef ITYPE
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#define ITYPE long
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#endif
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#ifdef DO_CALL
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extern ITYPE get_bits (ITYPE);
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#else
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#define get_bits(X) (X)
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#endif
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void test (ITYPE *bits, ITYPE n, TYPE one, TYPE_IN *p, TYPE_OUT *q)
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{
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TYPE x_00 = p[ 0];
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TYPE x_01 = p[ 1];
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TYPE x_02 = p[ 2];
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TYPE x_03 = p[ 3];
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TYPE x_04 = p[ 4];
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TYPE x_05 = p[ 5];
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TYPE x_06 = p[ 6];
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TYPE x_07 = p[ 7];
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TYPE x_08 = p[ 8];
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TYPE x_09 = p[ 9];
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TYPE x_10 = p[10];
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TYPE x_11 = p[11];
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TYPE x_12 = p[12];
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TYPE x_13 = p[13];
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TYPE x_14 = p[14];
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TYPE x_15 = p[15];
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TYPE x_16 = p[16];
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TYPE x_17 = p[17];
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TYPE x_18 = p[18];
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TYPE x_19 = p[19];
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TYPE x_20 = p[20];
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TYPE x_21 = p[21];
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TYPE x_22 = p[22];
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TYPE x_23 = p[23];
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TYPE x_24 = p[24];
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TYPE x_25 = p[25];
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TYPE x_26 = p[26];
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TYPE x_27 = p[27];
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TYPE x_28 = p[28];
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TYPE x_29 = p[29];
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TYPE x_30 = p[30];
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TYPE x_31 = p[31];
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TYPE x_32 = p[32];
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TYPE x_33 = p[33];
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TYPE x_34 = p[34];
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TYPE x_35 = p[35];
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TYPE x_36 = p[36];
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TYPE x_37 = p[37];
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TYPE x_38 = p[38];
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TYPE x_39 = p[39];
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TYPE x_40 = p[40];
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TYPE x_41 = p[41];
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TYPE x_42 = p[42];
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TYPE x_43 = p[43];
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TYPE x_44 = p[44];
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TYPE x_45 = p[45];
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TYPE x_46 = p[46];
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TYPE x_47 = p[47];
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TYPE x_48 = p[48];
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TYPE x_49 = p[49];
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ITYPE i;
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for (i = 0; i < n; i++)
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{
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ITYPE bit = get_bits (bits[i]);
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if ((bit & ((ITYPE)1) << 0) != 0) x_00 += one;
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if ((bit & ((ITYPE)1) << 1) != 0) x_01 += one;
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if ((bit & ((ITYPE)1) << 2) != 0) x_02 += one;
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if ((bit & ((ITYPE)1) << 3) != 0) x_03 += one;
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if ((bit & ((ITYPE)1) << 4) != 0) x_04 += one;
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if ((bit & ((ITYPE)1) << 5) != 0) x_05 += one;
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if ((bit & ((ITYPE)1) << 6) != 0) x_06 += one;
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if ((bit & ((ITYPE)1) << 7) != 0) x_07 += one;
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if ((bit & ((ITYPE)1) << 8) != 0) x_08 += one;
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if ((bit & ((ITYPE)1) << 9) != 0) x_09 += one;
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if ((bit & ((ITYPE)1) << 10) != 0) x_10 += one;
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if ((bit & ((ITYPE)1) << 11) != 0) x_11 += one;
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if ((bit & ((ITYPE)1) << 12) != 0) x_12 += one;
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if ((bit & ((ITYPE)1) << 13) != 0) x_13 += one;
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if ((bit & ((ITYPE)1) << 14) != 0) x_14 += one;
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if ((bit & ((ITYPE)1) << 15) != 0) x_15 += one;
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if ((bit & ((ITYPE)1) << 16) != 0) x_16 += one;
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if ((bit & ((ITYPE)1) << 17) != 0) x_17 += one;
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if ((bit & ((ITYPE)1) << 18) != 0) x_18 += one;
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if ((bit & ((ITYPE)1) << 19) != 0) x_19 += one;
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if ((bit & ((ITYPE)1) << 20) != 0) x_20 += one;
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if ((bit & ((ITYPE)1) << 21) != 0) x_21 += one;
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if ((bit & ((ITYPE)1) << 22) != 0) x_22 += one;
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if ((bit & ((ITYPE)1) << 23) != 0) x_23 += one;
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if ((bit & ((ITYPE)1) << 24) != 0) x_24 += one;
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if ((bit & ((ITYPE)1) << 25) != 0) x_25 += one;
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if ((bit & ((ITYPE)1) << 26) != 0) x_26 += one;
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if ((bit & ((ITYPE)1) << 27) != 0) x_27 += one;
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if ((bit & ((ITYPE)1) << 28) != 0) x_28 += one;
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if ((bit & ((ITYPE)1) << 29) != 0) x_29 += one;
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if ((bit & ((ITYPE)1) << 30) != 0) x_30 += one;
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if ((bit & ((ITYPE)1) << 31) != 0) x_31 += one;
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if ((bit & ((ITYPE)1) << 32) != 0) x_32 += one;
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if ((bit & ((ITYPE)1) << 33) != 0) x_33 += one;
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if ((bit & ((ITYPE)1) << 34) != 0) x_34 += one;
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if ((bit & ((ITYPE)1) << 35) != 0) x_35 += one;
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if ((bit & ((ITYPE)1) << 36) != 0) x_36 += one;
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if ((bit & ((ITYPE)1) << 37) != 0) x_37 += one;
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if ((bit & ((ITYPE)1) << 38) != 0) x_38 += one;
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if ((bit & ((ITYPE)1) << 39) != 0) x_39 += one;
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if ((bit & ((ITYPE)1) << 40) != 0) x_40 += one;
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if ((bit & ((ITYPE)1) << 41) != 0) x_41 += one;
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if ((bit & ((ITYPE)1) << 42) != 0) x_42 += one;
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if ((bit & ((ITYPE)1) << 43) != 0) x_43 += one;
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if ((bit & ((ITYPE)1) << 44) != 0) x_44 += one;
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if ((bit & ((ITYPE)1) << 45) != 0) x_45 += one;
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if ((bit & ((ITYPE)1) << 46) != 0) x_46 += one;
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if ((bit & ((ITYPE)1) << 47) != 0) x_47 += one;
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if ((bit & ((ITYPE)1) << 48) != 0) x_48 += one;
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if ((bit & ((ITYPE)1) << 49) != 0) x_49 += one;
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}
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q[ 0] = x_00;
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q[ 1] = x_01;
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q[ 2] = x_02;
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q[ 3] = x_03;
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q[ 4] = x_04;
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q[ 5] = x_05;
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q[ 6] = x_06;
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q[ 7] = x_07;
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q[ 8] = x_08;
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q[ 9] = x_09;
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q[10] = x_10;
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q[11] = x_11;
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q[12] = x_12;
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q[13] = x_13;
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q[14] = x_14;
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q[15] = x_15;
|
||||
q[16] = x_16;
|
||||
q[17] = x_17;
|
||||
q[18] = x_18;
|
||||
q[19] = x_19;
|
||||
|
||||
q[20] = x_20;
|
||||
q[21] = x_21;
|
||||
q[22] = x_22;
|
||||
q[23] = x_23;
|
||||
q[24] = x_24;
|
||||
q[25] = x_25;
|
||||
q[26] = x_26;
|
||||
q[27] = x_27;
|
||||
q[28] = x_28;
|
||||
q[29] = x_29;
|
||||
|
||||
q[30] = x_30;
|
||||
q[31] = x_31;
|
||||
q[32] = x_32;
|
||||
q[33] = x_33;
|
||||
q[34] = x_34;
|
||||
q[35] = x_35;
|
||||
q[36] = x_36;
|
||||
q[37] = x_37;
|
||||
q[38] = x_38;
|
||||
q[39] = x_39;
|
||||
|
||||
q[40] = x_40;
|
||||
q[41] = x_41;
|
||||
q[42] = x_42;
|
||||
q[43] = x_43;
|
||||
q[44] = x_44;
|
||||
q[45] = x_45;
|
||||
q[46] = x_46;
|
||||
q[47] = x_47;
|
||||
q[48] = x_48;
|
||||
q[49] = x_49;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mstw\M} } } */
|
||||
Loading…
Add table
Reference in a new issue