procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

* lra-assigns.c (assign_by_spills): Error out on spill failure.

Browse source 
From-SVN: r216059
This commit is contained in:
Eric Botcazou 2014-10-10 08:09:39 +00:00 • committed by Eric Botcazou
parent a6c631732f
commit bdf13188c0
2 changed files with 13 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
gcc/ChangeLog
View file

@ -1,3 +1,7 @@
2014-10-10 Eric Botcazou <ebotcazou@adacore.com>
* lra-assigns.c (assign_by_spills): Error out on spill failure.
2014-10-09 Markus Trippelsdorf <markus@trippelsdorf.de>
* pa-polymorphic-call.c (check_stmt_for_type_change): Move

16
gcc/lra-assigns.c
View file

@ -1286,10 +1286,9 @@ assign_by_spills (void)
break;
if (iter > 0)
{
/* We did not assign hard regs to reload pseudos after two
iteration. It means something is wrong with asm insn
constraints. Report it. */
bool asm_p = false;
/* We did not assign hard regs to reload pseudos after two iterations.
Either it's an asm and something is wrong with the constraints, or
we have run out of spill registers; error out in either case. */
bitmap_head failed_reload_insns;
bitmap_initialize (&failed_reload_insns, &reg_obstack);
@ -1299,7 +1298,7 @@ assign_by_spills (void)
bitmap_ior_into (&failed_reload_insns,
&lra_reg_info[regno].insn_bitmap);
/* Assign an arbitrary hard register of regno class to
avoid further trouble with the asm insns. */
avoid further trouble with this insn. */
bitmap_clear_bit (&all_spilled_pseudos, regno);
assign_hard_regno
(ira_class_hard_regs[regno_allocno_class_array[regno]][0],
@ -1310,7 +1309,6 @@ assign_by_spills (void)
insn = lra_insn_recog_data[u]->insn;
if (asm_noperands (PATTERN (insn)) >= 0)
{
asm_p = true;
error_for_asm (insn,
"%<asm%> operand has impossible constraints");
/* Avoid further trouble with this insn.
@ -1331,8 +1329,12 @@ assign_by_spills (void)
lra_set_insn_deleted (insn);
}
}
else
{
error ("unable to find a register to spill");
fatal_insn ("this is the insn:", insn);
}
}
lra_assert (asm_p);
break;
}
/* This is a very rare event. We can not assign a hard register