mips.md: Complete the unfinished R4000 multiply/shift errata workaround.
* config/mips/mips.md: Complete the unfinished R4000 multiply/shift errata workaround. Improve documentation. (hazard): Use TARGET_FIX_R4000 to decide whether an "imul" instruction has a hilo hazard. (mulsi3, mulsi3_internal, mulsi3_r4000): Use TARGET_FIX_R4000. (muldi3, muldi3_internal): Likewise. (muldi3_internal2): Remove, replacing with... (muldi3_mult3, muldi3_r4000): ...these new patterns. (mulsidi3): Take the errata into account. (mulsidi3_32bit): Remove, replacing with... (mulsidi3_32bit_internal, mulsidi3_32bit_r4000): ...these new patterns. (mulsidi3_64bit, mulsidi3_64bit_parts): Disable if TARGET_FIX_R4000. (umulsidi3): Take the errata into account. (umulsidi3_32bit): Remove, replacing with.. (umulsidi3_32bit_internal, umulsidi3_32bit_r4000): ...these patterns. (umulsi3_highpart, umulsi3_highpart_internal): Disable if TARGET_FIX_R4000. (smulsi3_highpart, smulsi3_highpart_internal): Likewise. (smuldi3_highpart, umuldi3_highpart): Likewise. * doc/invoke.texi: Document the errata workaround. From-SVN: r78622
This commit is contained in:
Maciej W. Rozycki
Richard Sandiford
parent
4649040309
commit
bddbfe5f67
3 changed files with 150 additions and 40 deletions
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@ -1,3 +1,26 @@
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2004-02-28 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
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* config/mips/mips.md: Complete the unfinished R4000
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multiply/shift errata workaround. Improve documentation.
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(hazard): Use TARGET_FIX_R4000 to decide whether an "imul" instruction
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has a hilo hazard.
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(mulsi3, mulsi3_internal, mulsi3_r4000): Use TARGET_FIX_R4000.
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(muldi3, muldi3_internal): Likewise.
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(muldi3_internal2): Remove, replacing with...
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(muldi3_mult3, muldi3_r4000): ...these new patterns.
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(mulsidi3): Take the errata into account.
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(mulsidi3_32bit): Remove, replacing with...
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(mulsidi3_32bit_internal, mulsidi3_32bit_r4000): ...these new patterns.
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(mulsidi3_64bit, mulsidi3_64bit_parts): Disable if TARGET_FIX_R4000.
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(umulsidi3): Take the errata into account.
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(umulsidi3_32bit): Remove, replacing with..
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(umulsidi3_32bit_internal, umulsidi3_32bit_r4000): ...these patterns.
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(umulsi3_highpart, umulsi3_highpart_internal): Disable if
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TARGET_FIX_R4000.
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(smulsi3_highpart, smulsi3_highpart_internal): Likewise.
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(smuldi3_highpart, umuldi3_highpart): Likewise.
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* doc/invoke.texi: Document the errata workaround.
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2004-02-28 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
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* config/mips/mips-protos.h (mips_idiv_insns): Declare.
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@ -233,7 +233,7 @@
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;; The r4000 multiplication patterns include an mflo instruction.
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(and (eq_attr "type" "imul")
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(ne (symbol_ref "TARGET_MIPS4000") (const_int 0)))
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(ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
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(const_string "hilo")
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(and (eq_attr "type" "hilo")
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@ -1420,9 +1420,51 @@
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(set_attr "length" "8")])
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;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
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;; a multiply is in progress, it may give an incorrect result. Avoid
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;; this by keeping the mflo with the mult on the R4000.
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;; The original R4000 has a cpu bug. If a double-word or a variable
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;; shift executes while an integer multiplication is in progress, the
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;; shift may give an incorrect result. Avoid this by keeping the mflo
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;; with the mult on the R4000.
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;;
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;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
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;; (also valid for MIPS R4000MC processors):
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;;
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;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
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;; this errata description.
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;; The following code sequence causes the R4000 to incorrectly
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;; execute the Double Shift Right Arithmetic 32 (dsra32)
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;; instruction. If the dsra32 instruction is executed during an
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;; integer multiply, the dsra32 will only shift by the amount in
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;; specified in the instruction rather than the amount plus 32
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;; bits.
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;; instruction 1: mult rs,rt integer multiply
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;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
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;; right arithmetic + 32
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;; Workaround: A dsra32 instruction placed after an integer
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;; multiply should not be one of the 11 instructions after the
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;; multiply instruction."
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;;
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;; and:
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;;
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;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
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;; the following description.
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;; All extended shifts (shift by n+32) and variable shifts (32 and
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;; 64-bit versions) may produce incorrect results under the
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;; following conditions:
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;; 1) An integer multiply is currently executing
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;; 2) These types of shift instructions are executed immediately
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;; following an integer divide instruction.
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;; Workaround:
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;; 1) Make sure no integer multiply is running wihen these
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;; instruction are executed. If this cannot be predicted at
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;; compile time, then insert a "mfhi" to R0 instruction
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;; immediately after the integer multiply instruction. This
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;; will cause the integer multiply to complete before the shift
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;; is executed.
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;; 2) Separate integer divide and these two classes of shift
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;; instructions by another instruction or a noop."
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;;
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;; These processors have PRId values of 0x00004220 and 0x00004300,
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;; respectively.
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(define_expand "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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@ -1432,7 +1474,7 @@
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{
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if (GENERATE_MULT3_SI || TARGET_MAD)
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emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
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else if (!TARGET_MIPS4000 || TARGET_MIPS16)
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else if (!TARGET_FIX_R4000)
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emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
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@ -1498,7 +1540,7 @@
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(mult:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))
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(clobber (match_scratch:SI 3 "=h"))]
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"!TARGET_MIPS4000 || TARGET_MIPS16"
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"!TARGET_FIX_R4000"
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"mult\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")])
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@ -1509,7 +1551,7 @@
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(match_operand:SI 2 "register_operand" "d")))
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(clobber (match_scratch:SI 3 "=h"))
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(clobber (match_scratch:SI 4 "=l"))]
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"TARGET_MIPS4000 && !TARGET_MIPS16"
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"TARGET_FIX_R4000"
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"mult\t%1,%2\;mflo\t%0"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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@ -1829,42 +1871,47 @@
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(match_operand:DI 2 "register_operand" "")))]
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"TARGET_64BIT"
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{
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if (GENERATE_MULT3_DI || TARGET_MIPS4000)
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emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
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else
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if (GENERATE_MULT3_DI)
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emit_insn (gen_muldi3_mult3 (operands[0], operands[1], operands[2]));
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else if (!TARGET_FIX_R4000)
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emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "muldi3_mult3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(mult:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "register_operand" "d")))
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(clobber (match_scratch:DI 3 "=h"))
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(clobber (match_scratch:DI 4 "=l"))]
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"TARGET_64BIT && GENERATE_MULT3_DI"
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"dmult\t%0,%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")])
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(define_insn "muldi3_internal"
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[(set (match_operand:DI 0 "register_operand" "=l")
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(mult:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "register_operand" "d")))
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(clobber (match_scratch:DI 3 "=h"))]
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"TARGET_64BIT && !TARGET_MIPS4000"
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"TARGET_64BIT && !TARGET_FIX_R4000"
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"dmult\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")])
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(define_insn "muldi3_internal2"
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(define_insn "muldi3_r4000"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(mult:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "register_operand" "d")))
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(clobber (match_scratch:DI 3 "=h"))
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(clobber (match_scratch:DI 4 "=l"))]
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"TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000)"
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{
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if (GENERATE_MULT3_DI)
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return "dmult\t%0,%1,%2";
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else
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return "dmult\t%1,%2\;mflo\t%0";
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}
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"TARGET_64BIT && TARGET_FIX_R4000"
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"dmult\t%1,%2\;mflo\t%0"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
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(const_int 4)
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(const_int 8)))])
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(set_attr "length" "8")])
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;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
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@ -1877,25 +1924,43 @@
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(clobber (scratch:DI))
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(clobber (scratch:DI))
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(clobber (scratch:DI))])]
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""
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"!TARGET_64BIT || !TARGET_FIX_R4000"
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{
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if (!TARGET_64BIT)
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{
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emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2]));
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if (!TARGET_FIX_R4000)
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emit_insn (gen_mulsidi3_32bit_internal (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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})
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(define_insn "mulsidi3_32bit"
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(define_insn "mulsidi3_32bit_internal"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
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"!TARGET_64BIT"
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"!TARGET_64BIT && !TARGET_FIX_R4000"
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"mult\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")])
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(define_insn "mulsidi3_32bit_r4000"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
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(clobber (match_scratch:DI 3 "=l"))
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(clobber (match_scratch:DI 4 "=h"))]
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"!TARGET_64BIT && TARGET_FIX_R4000"
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"mult\t%1,%2\;mflo\t%L0;mfhi\t%M0"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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(set_attr "length" "12")])
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(define_insn_and_split "*mulsidi3_64bit"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(mult:DI (match_operator:DI 1 "extend_operator"
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@ -1905,7 +1970,8 @@
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(clobber (match_scratch:DI 5 "=l"))
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(clobber (match_scratch:DI 6 "=h"))
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(clobber (match_scratch:DI 7 "=d"))]
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"TARGET_64BIT && GET_CODE (operands[1]) == GET_CODE (operands[2])"
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"TARGET_64BIT && !TARGET_FIX_R4000
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&& GET_CODE (operands[1]) == GET_CODE (operands[2])"
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"#"
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"&& reload_completed"
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[(parallel
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@ -1956,7 +2022,8 @@
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(match_operator:DI 4 "extend_operator" [(match_dup 2)])
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(match_operator:DI 5 "extend_operator" [(match_dup 3)]))
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(const_int 32)))]
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"TARGET_64BIT && GET_CODE (operands[4]) == GET_CODE (operands[5])"
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"TARGET_64BIT && !TARGET_FIX_R4000
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&& GET_CODE (operands[4]) == GET_CODE (operands[5])"
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{
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if (GET_CODE (operands[4]) == SIGN_EXTEND)
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return "mult\t%2,%3";
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@ -1975,26 +2042,43 @@
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(clobber (scratch:DI))
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(clobber (scratch:DI))
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(clobber (scratch:DI))])]
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""
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"!TARGET_64BIT || !TARGET_FIX_R4000"
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{
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if (!TARGET_64BIT)
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{
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emit_insn (gen_umulsidi3_32bit (operands[0], operands[1],
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operands[2]));
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if (!TARGET_FIX_R4000)
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emit_insn (gen_umulsidi3_32bit_internal (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_umulsidi3_32bit_r4000 (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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})
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(define_insn "umulsidi3_32bit"
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(define_insn "umulsidi3_32bit_internal"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
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"!TARGET_64BIT"
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"!TARGET_64BIT && !TARGET_FIX_R4000"
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"multu\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")])
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(define_insn "umulsidi3_32bit_r4000"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
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(clobber (match_scratch:DI 3 "=l"))
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(clobber (match_scratch:DI 4 "=h"))]
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"!TARGET_64BIT && TARGET_FIX_R4000"
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"multu\t%1,%2\;mflo\t%L0;mfhi\t%M0"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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(set_attr "length" "12")])
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;; Widening multiply with negation.
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(define_insn "*muls_di"
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[(set (match_operand:DI 0 "register_operand" "=x")
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@ -2064,7 +2148,7 @@
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "")))
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(const_int 32))))]
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""
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"ISA_HAS_MULHI || !TARGET_FIX_R4000"
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{
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if (ISA_HAS_MULHI)
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emit_insn (gen_umulsi3_highpart_mulhi_internal (operands[0], operands[1],
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@ -2083,7 +2167,7 @@
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(zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=l"))]
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"!ISA_HAS_MULHI"
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"!ISA_HAS_MULHI && !TARGET_FIX_R4000"
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"multu\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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@ -2131,7 +2215,7 @@
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "")))
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(const_int 32))))]
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""
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"ISA_HAS_MULHI || !TARGET_FIX_R4000"
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{
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if (ISA_HAS_MULHI)
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emit_insn (gen_smulsi3_highpart_mulhi_internal (operands[0], operands[1],
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@ -2150,7 +2234,7 @@
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(sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=l"))]
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"!ISA_HAS_MULHI"
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"!ISA_HAS_MULHI && !TARGET_FIX_R4000"
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"mult\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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@ -2199,7 +2283,7 @@
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(sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 "=l"))]
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"TARGET_64BIT"
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"TARGET_64BIT && !TARGET_FIX_R4000"
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"dmult\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")])
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@ -2213,7 +2297,7 @@
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(zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 "=l"))]
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"TARGET_64BIT"
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"TARGET_64BIT && !TARGET_FIX_R4000"
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"dmultu\t%1,%2"
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")])
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@ -8055,6 +8055,9 @@ Work around certain R4000 CPU errata:
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@item
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A double-word or a variable shift may give an incorrect result if executed
|
||||
immediately after starting an integer division.
|
||||
@item
|
||||
A double-word or a variable shift may give an incorrect result if executed
|
||||
while an integer multiplication is in progress.
|
||||
@end itemize
|
||||
|
||||
@item -mfix-sb1
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue