RISC-V: Quick and simple fixes to testcases that break due to reordering
The following test cases are easily fixed with small updates to the expected assembly order. Additionally make calling-convention testcases more robust PR target/113249 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Rearrange and adjust asm-checker times * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Rearrange assembly * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
This commit is contained in:
Edwin Lu
parent
67a29f99cc
commit
bc6b42666c
25 changed files with 140 additions and 62 deletions
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@ -143,12 +143,33 @@ DEF_RET1_ARG9 (v1024qi)
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DEF_RET1_ARG9 (v2048qi)
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DEF_RET1_ARG9 (v4096qi)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1qi tests: return value (lbu) and function prologue (sb)
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// 1 lbu per test, argnum sb's when args > 1
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/* { dg-final { scan-assembler-times {lbu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 35 } } */
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/* { dg-final { scan-assembler-times {sb\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v2qi test: return value (lhu) and function prologue (sh)
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// 1 lhu per test, argnum sh's when args > 1
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/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v4qi tests: return value (lw) and function prologue (sw)
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// 1 lw per test, argnum sw's when args > 1
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/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v8qi and v16qi tests: return value (ld) and function prologue (sd)
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// - 1 ld per v8qi and 2 ld per v16qi with args > 1
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// - 2 * argnum sd's per v8qi and 3 * argnum sd's per v16qi when argnum > 1
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v32-4096qi tests: return value (vse8.v)
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/* { dg-final { scan-assembler-times {vse8.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */
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// v1024-4096qi_ARG1 tests: return value (vse64.v)
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// for some reason ARG1 returns using vse64 instead of vse8
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */
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@ -133,10 +133,29 @@ DEF_RET1_ARG9 (v512hi)
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DEF_RET1_ARG9 (v1024hi)
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DEF_RET1_ARG9 (v2048hi)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1hi tests: return value (lhu) and function prologue (sh)
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// 1 lhu per test, argnum sh's when args > 1
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/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 33 } } */
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/* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v2hi tests: return value (lw) and function prologue (sw)
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// 1 lw per test, argnum sw's when args > 1
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/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v4hi and v8hi tests: return value (ld) and function prologue (sd)
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// - 1 ld per v4hi and 2 ld per v8hi with args > 1
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// - argnum sd's per v4hi when argnum > 1
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// - 2 * argnum sd's per v8hi when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v16-2048hi tests: return value (vse16.v)
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/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */
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// v512-2048qi_ARG1 tests: return value (vse64.v)
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// for some reason ARG1 returns using vse64 instead of vse16
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */
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@ -123,8 +123,24 @@ DEF_RET1_ARG9 (v256si)
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DEF_RET1_ARG9 (v512si)
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DEF_RET1_ARG9 (v1024si)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1si tests: return value (lw) and function prologue (sw)
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// 1 lw per test, argnum sw's when args > 1
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/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 31 } } */
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/* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v2si and v4si tests: return value (ld) and function prologue (sd)
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// - 1 ld per v2si and 2 ld per v4si with args > 1
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// - argnum sd's per v2si when argnum > 1
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// - 2 * argnum sd's per v4si when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v8-1024si tests: return value (vse32.v)
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/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */
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// 256-1024si tests: return value (vse64.v)
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// for some reason ARG1 returns using vse64 instead of vse32
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */
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@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128di)
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DEF_RET1_ARG9 (v256di)
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DEF_RET1_ARG9 (v512di)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1di and v2di tests: return value (ld) and function prologue (sd)
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// - 1 ld per v1di and 2 ld per v2di with args > 1
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// - argnum sd's per v1di when argnum > 1
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// - 2 * argnum sd's per v2di when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v4-512di tests: return value (vse64.v)
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */
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@ -133,9 +133,29 @@ DEF_RET1_ARG9 (v512hf)
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DEF_RET1_ARG9 (v1024hf)
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DEF_RET1_ARG9 (v2048hf)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1hf tests: return value (lhu) and function prologue (sh)
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// 1 lhu per test, argnum sh's when args > 1
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/* { dg-final { scan-assembler-times {lhu\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v2hf tests: return value (lw) and function prologue (sw)
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// 1 lw per test, argnum sw's when args > 1
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/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v4hf and v8hf tests: return value (ld) and function prologue (sd)
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// - 1 ld per v4hf and 2 ld per v8hf with args > 1
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// - argnum sd's per v4hf when argnum > 1
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// - 2 * argnum sd's per v8hf when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v16-2048hf tests: return value (vse16.v)
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/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */
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// v512-2048qf_ARG1 tests: return value (vse64.v)
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// for some reason ARG1 returns using vse64 instead of vse16
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */
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@ -123,7 +123,24 @@ DEF_RET1_ARG9 (v256sf)
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DEF_RET1_ARG9 (v512sf)
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DEF_RET1_ARG9 (v1024sf)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1sf tests: return value (lw) and function prologue (sw)
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// 1 lw per test, argnum sw's when args > 1
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/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */
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/* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
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// v2sf and v4sf tests: return value (ld) and function prologue (sd)
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// - 1 ld per v2sf and 2 ld per v4sf with args > 1
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// - argnum sd's per v2sf when argnum > 1
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// - 2 * argnum sd's per v4sf when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v8-1024sf tests: return value (vse32.v)
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/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */
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// 256-1024sf tests: return value (vse64.v)
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// for some reason ARG1 returns using vse64 instead of vse32
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */
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@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128df)
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DEF_RET1_ARG9 (v256df)
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DEF_RET1_ARG9 (v512df)
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// RET1_ARG0 tests
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/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */
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/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */
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// v1df and v2df tests: return value (ld) and function prologue (sd)
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// - 1 ld per v1df and 2 ld per v2df with args > 1
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// - argnum sd's per v1df when argnum > 1
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// - 2 * argnum sd's per v2df when argnum > 0
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/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */
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/* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */
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// v4-512df tests: return value (vse64.v)
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/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */
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@ -1,7 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
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// PR113249
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/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
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** f6:
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** ...
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** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
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** ...
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** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
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** ...
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
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** vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
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// PR113249
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/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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** f6:
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** ...
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** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
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** ...
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** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
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** ...
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** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
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** vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
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** vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
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// PR113249
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/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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** f6:
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** ...
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** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x)
|
|||
** f6:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
|
||||
// PR113249
|
||||
/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
#include "riscv_vector.h"
|
||||
|
||||
|
|
@ -28,9 +26,8 @@ void f1 (void * in, void *out)
|
|||
** f2:
|
||||
** ...
|
||||
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
** ...
|
||||
** ...
|
||||
** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
|
||||
** ...
|
||||
** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
|
||||
** vsll\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
|
||||
** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
|
||||
|
|
|
|||
|
|
@ -38,4 +38,4 @@ foo (int vl, int n, int m, int32_t *in, int32_t *out)
|
|||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\tzero,zero,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\tzero,a0,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue