spu.c (TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD): Defined.
* spu.c (TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD): Defined.
(spu_init_builtins): Mark the SPU_MASK_FOR_LOAD builtin decl as read
only.
(spu_expand_builtin_1): Handle the SPU_MASK_FOR_LOAD builtin.
(spu_builtin_mask_for_load): New.
* spu-builtins.def (SPU_MASK_FOR_LOAD): Define new builtin.
* spu.md (UNSPEC_SPU_REALIGN_LOAD, UNSPEC_SPU_MASK_FOR_LOAD):New.
(vec_realign_load_<mode>, spu_lvsr): New.
Co-Authored-By: Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
From-SVN: r119857
This commit is contained in:
Dorit Nuzman
Dorit Nuzman
parent
f4f7486bcf
commit
bbea461bd9
6 changed files with 110 additions and 2 deletions
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@ -1,3 +1,15 @@
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2006-12-14 Dorit Nuzman <dorit@il.ibm.com>
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Trevor Smigiel <trevor_smigiel@playstation.sony.com>
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* spu.c (TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD): Defined.
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(spu_init_builtins): Mark the SPU_MASK_FOR_LOAD builtin decl as read
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only.
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(spu_expand_builtin_1): Handle the SPU_MASK_FOR_LOAD builtin.
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(spu_builtin_mask_for_load): New.
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* spu-builtins.def (SPU_MASK_FOR_LOAD): Define new builtin.
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* spu.md (UNSPEC_SPU_REALIGN_LOAD, UNSPEC_SPU_MASK_FOR_LOAD):New.
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(vec_realign_load_<mode>, spu_lvsr): New.
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2006-12-13 Ian Lance Taylor <iant@google.com>
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PR c++/19564
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@ -246,6 +246,7 @@ DEF_BUILTIN (SPU_CMPABSEQ, CODE_FOR_cmeq_v4sf, "spu_cmpabseq", B_INSN,
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DEF_BUILTIN (SPU_CMPABSGT, CODE_FOR_cmgt_v4sf, "spu_cmpabsgt", B_INSN, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
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DEF_BUILTIN (SPU_IDISABLE, CODE_FOR_spu_idisable, "spu_idisable", B_INSN, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_IENABLE, CODE_FOR_spu_ienable, "spu_ienable", B_INSN, _A1(SPU_BTI_VOID))
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DEF_BUILTIN (SPU_MASK_FOR_LOAD, CODE_FOR_spu_lvsr, "spu_lvsr", B_INSN, _A2(SPU_BTI_V16QI, SPU_BTI_PTR))
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/* definitions to support overloaded generic builtin functions: */
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@ -130,6 +130,7 @@ static void spu_init_libfuncs (void);
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static bool spu_return_in_memory (tree type, tree fntype);
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static void fix_range (const char *);
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static void spu_encode_section_info (tree, rtx, int);
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static tree spu_builtin_mask_for_load (void);
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extern const char *reg_names[];
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rtx spu_compare_op0, spu_compare_op1;
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@ -248,6 +249,9 @@ const struct attribute_spec spu_attribute_table[];
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#undef TARGET_ENCODE_SECTION_INFO
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#define TARGET_ENCODE_SECTION_INFO spu_encode_section_info
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#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
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#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD spu_builtin_mask_for_load
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Sometimes certain combinations of command options do not make sense
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@ -4288,6 +4292,8 @@ spu_init_builtins (void)
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d->fndecl =
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add_builtin_function (name, p, END_BUILTINS + i, BUILT_IN_MD,
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NULL, NULL_TREE);
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if (d->fcode == SPU_MASK_FOR_LOAD)
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TREE_READONLY (d->fndecl) = 1;
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}
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}
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@ -4843,6 +4849,31 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
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i++;
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}
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if (d->fcode == SPU_MASK_FOR_LOAD)
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{
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enum machine_mode mode = insn_data[icode].operand[1].mode;
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tree arg;
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rtx addr, op, pat;
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/* get addr */
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arg = TREE_VALUE (arglist);
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gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
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op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
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addr = memory_address (mode, op);
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/* negate addr */
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op = gen_reg_rtx (GET_MODE (addr));
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emit_insn (gen_rtx_SET (VOIDmode, op,
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gen_rtx_NEG (GET_MODE (addr), addr)));
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op = gen_rtx_MEM (mode, op);
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pat = GEN_FCN (icode) (target, op);
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if (!pat)
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return 0;
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emit_insn (pat);
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return target;
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}
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/* Ignore align_hint, but still expand it's args in case they have
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side effects. */
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if (icode == CODE_FOR_spu_align_hint)
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@ -4962,3 +4993,11 @@ spu_expand_builtin (tree exp,
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abort ();
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}
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/* Implement targetm.vectorize.builtin_mask_for_load. */
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static tree
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spu_builtin_mask_for_load (void)
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{
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struct spu_builtin_description *d = &spu_builtins[SPU_MASK_FOR_LOAD];
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gcc_assert (d);
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return d->fndecl;
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}
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@ -142,7 +142,10 @@
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(UNSPEC_MTSPR 45)
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(UNSPEC_RDCH 46)
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(UNSPEC_RCHCNT 47)
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(UNSPEC_WRCH 48)])
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(UNSPEC_WRCH 48)
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(UNSPEC_SPU_REALIGN_LOAD 49)
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(UNSPEC_SPU_MASK_FOR_LOAD 50)
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])
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(include "predicates.md")
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(include "constraints.md")
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@ -3374,3 +3377,53 @@ selb\t%0,%4,%0,%3"
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emit_insn (gen_selb (operands[0], operands[1], operands[2], mask));
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DONE;
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}")
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(define_expand "vec_realign_load_<mode>"
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[(set (match_operand:ALL 0 "register_operand" "=r")
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(unspec:ALL [(match_operand:ALL 1 "register_operand" "r")
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(match_operand:ALL 2 "register_operand" "r")
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(match_operand:TI 3 "register_operand" "r")] UNSPEC_SPU_REALIGN_LOAD))]
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""
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"
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{
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emit_insn (gen_shufb (operands[0], operands[1], operands[2], operands[3]));
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DONE;
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}")
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(define_expand "spu_lvsr"
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[(set (match_operand:V16QI 0 "register_operand" "")
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(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_SPU_MASK_FOR_LOAD))]
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""
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"
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{
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rtx addr;
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rtx offset = gen_reg_rtx (V8HImode);
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rtx addr_bits = gen_reg_rtx (SImode);
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rtx addr_bits_vec = gen_reg_rtx (V8HImode);
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rtx splatqi = gen_reg_rtx (TImode);
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rtx result = gen_reg_rtx (V8HImode);
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unsigned char arr[16] = {
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
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unsigned char arr2[16] = {
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0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
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0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
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emit_move_insn (offset, array_to_constant (V8HImode, arr));
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emit_move_insn (splatqi, array_to_constant (TImode, arr2));
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gcc_assert (GET_CODE (operands[1]) == MEM);
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addr = force_reg (Pmode, XEXP (operands[1], 0));
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emit_insn (gen_andsi3 (addr_bits, addr, GEN_INT (0xF)));
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emit_insn (gen_shufb (addr_bits_vec, addr_bits, addr_bits, splatqi));
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/* offset - (addr & 0xF)
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It is safe to use a single sfh, because each byte of offset is > 15 and
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each byte of addr is <= 15. */
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emit_insn (gen_subv8hi3 (result, offset, addr_bits_vec));
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result = simplify_gen_subreg (V16QImode, result, V8HImode, 0);
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emit_move_insn (operands[0], result);
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DONE;
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}")
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@ -1,3 +1,7 @@
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2006-12-14 Dorit Nuzman <dorit@il.ibm.com>
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* lib/target-supports.exp (vect_no_align): Remove spu.
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2006-12-13 Ian Lance Taylor <iant@google.com>
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PR c++/19564
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@ -1789,7 +1789,6 @@ proc check_effective_target_vect_no_align { } {
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} else {
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set et_vect_no_align_saved 0
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if { [istarget mipsisa64*-*-*]
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|| [istarget spu-*-*]
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|| [istarget sparc*-*-*]
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|| [istarget ia64-*-*] } {
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set et_vect_no_align_saved 1
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