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[nvptx] Add bar.warp.sync

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On a GT 1030 (sm_61), with driver version 470.94 I run into:
...
FAIL: libgomp.oacc-c/../libgomp.oacc-c-c++-common/parallel-dims.c \
  -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none \
  -O2 execution test
...
which minimizes to the same test-case as listed in commit "[nvptx] Update
default ptx isa to 6.3".

The first divergent branch looks like:
...
  {
    .reg .u32 %x;
    mov.u32 %x,%tid.x;
    setp.ne.u32 %r59,%x,0;
  }
  @ %r59 bra $L15;
  mov.u64 %r48,%ar0;
  mov.u32 %r22,2;
  ld.u64 %r53,[%r48];
  mov.u32 %r55,%r22;
  mov.u32 %r54,1;
 $L15:
...
and when inspecting the generated SASS, the branch is not setup as a divergent
branch, but instead as a regular branch.

This causes us to execute a shfl.sync insn in divergent mode, which is likely
to cause trouble given a remark in the ptx isa version 6.3, which mentions
that for .target sm_6x or below, all threads must excute the same
shfl.sync instruction in convergence.

Fix this by placing a "bar.warp.sync 0xffffffff" at the desired convergence
point (in the example above, after $L15).

Tested on x86_64 with nvptx accelerator.

gcc/ChangeLog:

2022-01-31  Tom de Vries  <tdevries@suse.de>

	* config/nvptx/nvptx.cc (nvptx_single): Use nvptx_warpsync.
	* config/nvptx/nvptx.md (define_c_enum "unspecv"): Add
	UNSPECV_WARPSYNC.
	(define_insn "nvptx_warpsync"): New define_insn.
This commit is contained in:
Tom de Vries 2022-01-27 15:03:59 +01:00
parent 8ff0669f6d
commit bba61d403d
2 changed files with 14 additions and 0 deletions
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7
gcc/config/nvptx/nvptx.cc
View file

@ -4598,6 +4598,7 @@ nvptx_single (unsigned mask, basic_block from, basic_block to)
rtx_insn *neuter_start = NULL;
rtx_insn *worker_label = NULL, *vector_label = NULL;
rtx_insn *worker_jump = NULL, *vector_jump = NULL;
rtx_insn *warp_sync = NULL;
for (mode = GOMP_DIM_WORKER; mode <= GOMP_DIM_VECTOR; mode++)
if (GOMP_DIM_MASK (mode) & skip_mask)
{
@ -4630,11 +4631,15 @@ nvptx_single (unsigned mask, basic_block from, basic_block to)
if (tail_branch)
{
label_insn = emit_label_before (label, before);
if (TARGET_PTX_6_0 && mode == GOMP_DIM_VECTOR)
warp_sync = emit_insn_after (gen_nvptx_warpsync (), label_insn);
before = label_insn;
}
else
{
label_insn = emit_label_after (label, tail);
if (TARGET_PTX_6_0 && mode == GOMP_DIM_VECTOR)
warp_sync = emit_insn_after (gen_nvptx_warpsync (), label_insn);
if ((mode == GOMP_DIM_VECTOR || mode == GOMP_DIM_WORKER)
&& CALL_P (tail) && find_reg_note (tail, REG_NORETURN, NULL))
emit_insn_after (gen_exit (), label_insn);
@ -4702,6 +4707,8 @@ nvptx_single (unsigned mask, basic_block from, basic_block to)
setp.ne.u32 %rcond,%rcondu32,0;
*/
rtx_insn *label = PREV_INSN (tail);
if (label == warp_sync)
label = PREV_INSN (label);
gcc_assert (label && LABEL_P (label));
rtx tmp = gen_reg_rtx (BImode);
emit_insn_before (gen_movbi (tmp, const0_rtx),

7
gcc/config/nvptx/nvptx.md
View file

@ -56,6 +56,7 @@
UNSPECV_CAS
UNSPECV_XCHG
UNSPECV_BARSYNC
UNSPECV_WARPSYNC
UNSPECV_MEMBAR
UNSPECV_MEMBAR_CTA
UNSPECV_MEMBAR_GL
@ -1978,6 +1979,12 @@
}
[(set_attr "predicable" "false")])
(define_insn "nvptx_warpsync"
[(unspec_volatile [(const_int 0)] UNSPECV_WARPSYNC)]
"TARGET_PTX_6_0"
"\\tbar.warp.sync\\t0xffffffff;"
[(set_attr "predicable" "false")])
(define_expand "memory_barrier"
[(set (match_dup 0)
(unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMBAR))]