AVX-512. Add reduce, range, fpclass insn patterns.
gcc/ * config/i386/i386.c (ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round, avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask, avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask, avx512dq_rangepv4sf_mask. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS, UNSPEC_RANGE. (define_insn "<mask_codefor>reducep<mode><mask_name>"): New. (define_insn "reduces<mode>"): Ditto. (define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"): Ditto. (define_insn "avx512dq_ranges<mode><round_saeonly_name>"): Ditto. (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"): Ditto. (define_insn "avx512dq_vmfpclass<mode>"): Ditto.. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r215107
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
b040ded3c6
commit
b982628645
3 changed files with 121 additions and 0 deletions
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@ -1,3 +1,28 @@
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2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/i386.c
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(ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round,
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avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask,
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avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask,
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avx512dq_rangepv4sf_mask.
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* config/i386/sse.md
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(define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS,
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UNSPEC_RANGE.
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(define_insn "<mask_codefor>reducep<mode><mask_name>"): New.
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(define_insn "reduces<mode>"): Ditto.
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(define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"):
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Ditto.
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(define_insn "avx512dq_ranges<mode><round_saeonly_name>"): Ditto.
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(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"): Ditto.
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(define_insn "avx512dq_vmfpclass<mode>"): Ditto..
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2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -34090,6 +34090,12 @@ ix86_expand_args_builtin (const struct builtin_description *d,
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case CODE_FOR_avx512vl_getmantv4df_mask:
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case CODE_FOR_avx512vl_getmantv4sf_mask:
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case CODE_FOR_avx512vl_getmantv2df_mask:
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case CODE_FOR_avx512dq_rangepv8df_mask_round:
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case CODE_FOR_avx512dq_rangepv16sf_mask_round:
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case CODE_FOR_avx512dq_rangepv4df_mask:
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case CODE_FOR_avx512dq_rangepv8sf_mask:
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case CODE_FOR_avx512dq_rangepv2df_mask:
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case CODE_FOR_avx512dq_rangepv4sf_mask:
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error ("the last argument must be a 4-bit immediate");
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return const0_rtx;
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@ -128,6 +128,11 @@
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UNSPEC_SHA256MSG1
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UNSPEC_SHA256MSG2
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UNSPEC_SHA256RNDS2
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;; For AVX512DQ support
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UNSPEC_REDUCE
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UNSPEC_FPCLASS
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UNSPEC_RANGE
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])
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(define_c_enum "unspecv" [
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@ -2330,6 +2335,34 @@
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DONE;
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})
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(define_insn "<mask_codefor>reducep<mode><mask_name>"
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[(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
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(unspec:VF_AVX512VL
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[(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "vm")
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(match_operand:SI 2 "const_0_to_255_operand")]
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UNSPEC_REDUCE))]
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"TARGET_AVX512DQ"
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"vreduce<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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(define_insn "reduces<mode>"
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[(set (match_operand:VF_128 0 "register_operand" "=v")
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(vec_merge:VF_128
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(unspec:VF_128
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[(match_operand:VF_128 1 "register_operand" "v")
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(match_operand:VF_128 2 "nonimmediate_operand" "vm")
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(match_operand:SI 3 "const_0_to_255_operand")]
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UNSPEC_REDUCE)
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512DQ"
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"vreduce<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel floating point comparisons
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@ -16754,6 +16787,63 @@
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(set_attr "memory" "none,load")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"
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[(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
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(unspec:VF_AVX512VL
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[(match_operand:VF_AVX512VL 1 "register_operand" "v")
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(match_operand:VF_AVX512VL 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
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(match_operand:SI 3 "const_0_to_15_operand")]
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UNSPEC_RANGE))]
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"TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
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"vrange<ssemodesuffix>\t{<round_saeonly_mask_op4>%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3<round_saeonly_mask_op4>}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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(define_insn "avx512dq_ranges<mode><round_saeonly_name>"
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[(set (match_operand:VF_128 0 "register_operand" "=v")
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(vec_merge:VF_128
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(unspec:VF_128
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[(match_operand:VF_128 1 "register_operand" "v")
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(match_operand:VF_128 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
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(match_operand:SI 3 "const_0_to_15_operand")]
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UNSPEC_RANGE)
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512DQ"
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"vrange<ssescalarmodesuffix>\t{<round_saeonly_op4>%3, %2, %1, %0|%0, %1, %2, %3<round_saeonly_op4>}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(unspec:<avx512fmaskmode>
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[(match_operand:VF_AVX512VL 1 "register_operand" "v")
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(match_operand:QI 2 "const_0_to_255_operand" "n")]
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UNSPEC_FPCLASS))]
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"TARGET_AVX512DQ"
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"vfpclass<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
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[(set_attr "type" "sse")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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(define_insn "avx512dq_vmfpclass<mode>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(and:<avx512fmaskmode>
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(unspec:<avx512fmaskmode>
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[(match_operand:VF_128 1 "register_operand" "v")
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(match_operand:QI 2 "const_0_to_255_operand" "n")]
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UNSPEC_FPCLASS)
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(const_int 1)))]
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"TARGET_AVX512DQ"
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"vfpclass<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
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[(set_attr "type" "sse")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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(define_insn "<avx512>_getmant<mode><mask_name><round_saeonly_name>"
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[(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
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(unspec:VF_AVX512VL
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