[14 regression] Fix insn types in risc-v port
So one of the broad goals we've had over the last few months has been to ensure that every insn has a scheduling type and that every insn is associated with an insn reservation in the scheduler. This avoids some amazingly bad behavior in the scheduler. I won't go through the gory details. I was recently analyzing a code quality regression with dhrystone (ugh!) and one of the issues was poor scheduling which lengthened the lifetime of a pseudo and ultimately resulted in needing an additional callee saved register save/restore. This was ultimately tracked down incorrect types on a few patterns. So I did an audit of all the patterns that had types added/changed as part of this effort and found a variety of problems, primarily in the various move patterns and extension patterns. This is a regression relative to gcc-13. Naturally the change in types affects scheduling, which in turn changes the precise code we generate and causes some testsuite fallout. I considered updating the regexps since the change in the resulting output is pretty consistent. But of course the test would still be sensitive to things like load latency. So instead I just turned off the 2nd phase scheduler in the affected tests. Bootstrapped and regression tested on rv64gc-linux-gnu. gcc * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix type attribute. (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. (movdi_32bit, movdi_64bit, movsi_internal): Likewise. (movhi_internal, movqi_internal): Likewise. (movsf_softfloat, movsf_hardfloat): Likewise. (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. (movdf_softfloat): Likewise. gcc/testsuite * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off second phase scheduler. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
This commit is contained in:
Jeff Law
parent
e15ef78e4a
commit
b7b387e120
8 changed files with 21 additions and 21 deletions
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@ -1836,7 +1836,7 @@
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andi\t%0,%1,0xff
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lbu\t%0,%1"
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[(set_attr "move_type" "andi,load")
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(set_attr "type" "multi")
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(set_attr "type" "arith,load")
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(set_attr "mode" "<SUPERQI:MODE>")])
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;;
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@ -1861,7 +1861,7 @@
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sext.w\t%0,%1
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lw\t%0,%1"
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[(set_attr "move_type" "move,load")
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(set_attr "type" "multi")
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(set_attr "type" "move,load")
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(set_attr "mode" "DI")])
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(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
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@ -1938,7 +1938,7 @@
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|| reg_or_0_operand (operands[1], HFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "mode" "HF")])
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(define_insn "*movhf_softfloat"
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@ -1949,7 +1949,7 @@
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|| reg_or_0_operand (operands[1], HFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fmove,move,load,store,mtc,mfc")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,move,load,store,mtc,mfc")
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(set_attr "mode" "HF")])
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(define_insn "*movhf_softfloat_boxing"
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@ -2182,7 +2182,7 @@
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
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(set_attr "mode" "DI")
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(set_attr "type" "move")
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(set_attr "type" "move,move,load,store,move,fpload,move,fmove,fpstore,move")
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(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
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(define_insn "*movdi_64bit"
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@ -2194,7 +2194,7 @@
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
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(set_attr "mode" "DI")
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(set_attr "type" "move")
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(set_attr "type" "move,move,load,store,mtc,fpload,mfc,fmove,fpstore,move")
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(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
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;; 32-bit Integer moves
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@ -2217,7 +2217,7 @@
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
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(set_attr "mode" "SI")
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(set_attr "type" "move")
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(set_attr "type" "move,move,load,store,mtc,fpload,mfc,fpstore,move")
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(set_attr "ext" "base,base,base,base,f,f,f,f,vector")])
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;; 16-bit Integer moves
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@ -2244,7 +2244,7 @@
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
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(set_attr "mode" "HI")
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(set_attr "type" "move")
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(set_attr "type" "move,move,load,store,mtc,mfc,move")
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(set_attr "ext" "base,base,base,base,f,f,vector")])
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;; HImode constant generation; see riscv_move_integer for details.
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@ -2288,7 +2288,7 @@
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
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(set_attr "mode" "QI")
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(set_attr "type" "move")
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(set_attr "type" "move,move,load,store,mtc,mfc,move")
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(set_attr "ext" "base,base,base,base,f,f,vector")])
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;; 32-bit floating point moves
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@ -2310,7 +2310,7 @@
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|| reg_or_0_operand (operands[1], SFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "mode" "SF")])
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(define_insn "*movsf_softfloat"
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@ -2321,7 +2321,7 @@
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|| reg_or_0_operand (operands[1], SFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "move,load,store")
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(set_attr "mode" "SF")])
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;; 64-bit floating point moves
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@ -2346,7 +2346,7 @@
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|| reg_or_0_operand (operands[1], DFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "mode" "DF")])
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(define_insn "*movdf_hardfloat_rv64"
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@ -2357,7 +2357,7 @@
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|| reg_or_0_operand (operands[1], DFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
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(set_attr "mode" "DF")])
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(define_insn "*movdf_softfloat"
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@ -2368,7 +2368,7 @@
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|| reg_or_0_operand (operands[1], DFmode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,load,store")
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(set_attr "type" "fmove")
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(set_attr "type" "fmove,fpload,fpstore")
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(set_attr "mode" "DF")])
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(define_insn "movsidf2_low_rv32"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
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/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */
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#include "def.h"
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