diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index ef3310605ca..8446dd7f964 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2738,17 +2738,6 @@
   [(set_attr "type" "neon_fp_minmax_s<q>")]
 )
 
-;; Vector forms for the IEEE-754 fmax()/fmin() functions
-(define_insn "<fmaxmin><mode>3"
-  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
-	(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
-		       (match_operand:VCVTF 2 "s_register_operand" "w")]
-		       VMAXMINFNM))]
-  "TARGET_NEON && TARGET_VFP5"
-  "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
-  [(set_attr "type" "neon_fp_minmax_s<q>")]
-)
-
 (define_expand "neon_vpadd<mode>"
   [(match_operand:VD 0 "s_register_operand")
    (match_operand:VD 1 "s_register_operand")
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 204205cb0b7..a485d057f0f 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -137,6 +137,17 @@
    "ARM_HAVE_<MODE>_ARITH"
 )
 
+;; Vector forms for the IEEE-754 fmax()/fmin() functions
+;; Fixme: Should be enabled for MVE as well, but currently that uses an
+;; incompatible expasion.
+(define_expand "<fmaxmin><mode>3"
+  [(set (match_operand:VF 0 "s_register_operand" "")
+	(unspec:VF [(match_operand:VF 1 "s_register_operand")
+		    (match_operand:VF 2 "s_register_operand")]
+		   VMAXMINFNM))]
+  "TARGET_NEON && TARGET_VFP5 && ARM_HAVE_<MODE>_ARITH"
+)
+
 (define_expand "vec_perm<mode>"
   [(match_operand:VE 0 "s_register_operand")
    (match_operand:VE 1 "s_register_operand")
diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin-2.c b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c
new file mode 100644
index 00000000000..a9990e19243
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_hard_ok } */
+/* { dg-options "-O2 -fno-inline" } */
+/* { dg-add-options arm_arch_v8a_hard } */
+
+#include "fmaxmin.x"
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin.c b/gcc/testsuite/gcc.target/arm/fmaxmin.c
index 5a6fb804e3d..7f30c1237ab 100644
--- a/gcc/testsuite/gcc.target/arm/fmaxmin.c
+++ b/gcc/testsuite/gcc.target/arm/fmaxmin.c
@@ -1,13 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_v8_neon_hw } */
-/* { dg-options "-O2 -fno-inline -march=armv8-a -save-temps" } */
+/* { dg-options "-O2 -fno-inline" } */
 /* { dg-add-options arm_v8_neon } */
 
 #include "fmaxmin.x"
-
-/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
-/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
-
-/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
-/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
-