amdgcn: Use correct offset mode for gather/scatter
The scatter/gather pattern names changed for GCC 10, but I hadn't noticed. This switches the patterns to the new offset mode scheme. 2020-02-21 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ... (gather_load<mode>v64si): ... this and set operand 2 to V64SI. (scatter_store<mode>): Rename to ... (scatter_store<mode>v64si): ... this and set operand 1 to V64SI. (scatter<mode>_exec): Delete. Move contents ... (mask_scatter_store<mode>): ... here, and rename that to ... (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI. Remove mode conversion. (mask_gather_load<mode>): Rename to ... (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI. Remove mode conversion. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
This commit is contained in:
Andrew Stubbs
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4d6bf96b58
commit
b5fb73b6be
3 changed files with 36 additions and 66 deletions
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@ -1,3 +1,18 @@
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2020-02-21 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
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(gather_load<mode>v64si): ... this and set operand 2 to V64SI.
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(scatter_store<mode>): Rename to ...
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(scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
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(scatter<mode>_exec): Delete. Move contents ...
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(mask_scatter_store<mode>): ... here, and rename that to ...
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(mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
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Remove mode conversion.
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(mask_gather_load<mode>): Rename to ...
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(mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
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Remove mode conversion.
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* config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
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2020-02-21 Martin Jambor <mjambor@suse.cz>
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PR tree-optimization/93845
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@ -679,10 +679,10 @@
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;; fields normally found in a MEM.
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;; - Multiple forms of address expression are supported, below.
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(define_expand "gather_load<mode>"
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(define_expand "gather_load<mode>v64si"
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[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
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(match_operand:DI 1 "register_operand")
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(match_operand 2 "register_operand")
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(match_operand:V64SI 2 "register_operand")
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(match_operand 3 "immediate_operand")
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(match_operand:SI 4 "gcn_alu_operand")]
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""
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@ -811,9 +811,9 @@
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[(set_attr "type" "flat")
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(set_attr "length" "12")])
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(define_expand "scatter_store<mode>"
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(define_expand "scatter_store<mode>v64si"
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[(match_operand:DI 0 "register_operand")
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(match_operand 1 "register_operand")
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(match_operand:V64SI 1 "register_operand")
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(match_operand 2 "immediate_operand")
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(match_operand:SI 3 "gcn_alu_operand")
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(match_operand:VEC_ALLREG_MODE 4 "register_operand")]
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@ -833,34 +833,6 @@
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DONE;
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})
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(define_expand "scatter<mode>_exec"
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[(match_operand:DI 0 "register_operand")
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(match_operand 1 "register_operand")
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(match_operand 2 "immediate_operand")
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(match_operand:SI 3 "gcn_alu_operand")
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(match_operand:VEC_ALLREG_MODE 4 "register_operand")
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(match_operand:DI 5 "gcn_exec_reg_operand")]
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""
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{
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operands[5] = force_reg (DImode, operands[5]);
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rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0],
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operands[1], operands[3],
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INTVAL (operands[2]), operands[5]);
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if (GET_MODE (addr) == V64DImode)
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emit_insn (gen_scatter<mode>_insn_1offset_exec (addr, const0_rtx,
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operands[4], const0_rtx,
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const0_rtx,
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operands[5]));
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else
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emit_insn (gen_scatter<mode>_insn_2offsets_exec (operands[0], addr,
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const0_rtx, operands[4],
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const0_rtx, const0_rtx,
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operands[5]));
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DONE;
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})
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; Allow any address expression
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(define_expand "scatter<mode>_expr<exec_scatter>"
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[(set (mem:BLK (scratch))
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@ -2795,10 +2767,10 @@
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DONE;
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})
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(define_expand "mask_gather_load<mode>"
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(define_expand "mask_gather_load<mode>v64si"
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[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
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(match_operand:DI 1 "register_operand")
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(match_operand 2 "register_operand")
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(match_operand:V64SI 2 "register_operand")
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(match_operand 3 "immediate_operand")
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(match_operand:SI 4 "gcn_alu_operand")
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(match_operand:DI 5 "")]
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@ -2806,16 +2778,6 @@
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{
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rtx exec = force_reg (DImode, operands[5]);
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/* TODO: more conversions will be needed when more types are vectorized. */
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if (GET_MODE (operands[2]) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_truncv64div64si2_exec (tmp, operands[2],
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gcn_gen_undef (V64SImode),
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exec));
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operands[2] = tmp;
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}
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rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[1],
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operands[2], operands[4],
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INTVAL (operands[3]), exec);
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@ -2836,9 +2798,9 @@
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DONE;
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})
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(define_expand "mask_scatter_store<mode>"
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(define_expand "mask_scatter_store<mode>v64si"
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[(match_operand:DI 0 "register_operand")
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(match_operand 1 "register_operand")
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(match_operand:V64SI 1 "register_operand")
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(match_operand 2 "immediate_operand")
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(match_operand:SI 3 "gcn_alu_operand")
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(match_operand:VEC_ALLREG_MODE 4 "register_operand")
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@ -2847,18 +2809,20 @@
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{
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rtx exec = force_reg (DImode, operands[5]);
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/* TODO: more conversions will be needed when more types are vectorized. */
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if (GET_MODE (operands[1]) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_truncv64div64si2_exec (tmp, operands[1],
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gcn_gen_undef (V64SImode),
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exec));
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operands[1] = tmp;
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}
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rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0],
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operands[1], operands[3],
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INTVAL (operands[2]), exec);
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emit_insn (gen_scatter<mode>_exec (operands[0], operands[1], operands[2],
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operands[3], operands[4], exec));
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if (GET_MODE (addr) == V64DImode)
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emit_insn (gen_scatter<mode>_insn_1offset_exec (addr, const0_rtx,
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operands[4], const0_rtx,
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const0_rtx,
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exec));
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else
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emit_insn (gen_scatter<mode>_insn_2offsets_exec (operands[0], addr,
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const0_rtx, operands[4],
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const0_rtx, const0_rtx,
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exec));
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DONE;
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})
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@ -1861,15 +1861,6 @@ rtx
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gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets, rtx scale,
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bool unsigned_p, rtx exec)
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{
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/* Convert the offsets to V64SImode.
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TODO: more conversions will be needed when more types are vectorized. */
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if (GET_MODE (offsets) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_truncv64div64si2 (tmp, offsets));
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offsets = tmp;
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}
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rtx tmpsi = gen_reg_rtx (V64SImode);
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rtx tmpdi = gen_reg_rtx (V64DImode);
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rtx undefsi = exec ? gcn_gen_undef (V64SImode) : NULL;
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